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Intellectual Property Cores
News Release from: Denali Software | Subject: Databahn DDR memory controller IP
Edited by the Electronicstalk Editorial
Team on 10 March 2008
Network processors accelerated to market
IPs accelerate designers' ability to design in DDR2/3 and PCIe, lower their integration risk and speed their time to market for delivering their network processors in silicon.
Netronome Systems has selected Denali's Databahn DDR memory controller IP, integrated DDR hard PHY and PCI Express (PCIe) controller IP for its high-performance network processors Netronome's next-generation high-end network flow processors enable manufacturers to accelerate application level processing in several Layer 2-7 markets including switching and routing, network security, broadband access, test and measurement and wireless markets
This article was originally published on Electronicstalk on 17 May 2007 at 8.00am (UK)
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Denali's design controller IPs accelerate Netronome's designers' ability to design in DDR2/3 and PCIe, lower their integration risk and speed their time to market for delivering their network processors in silicon.
"Working with a leading IP provider, such as Denali Software, who provides a comprehensive tailored data solution and verification environment, will helps us achieve our time to market goals in a cost-effective way", says Jim Finnegan, Senior Vice President of Engineering at Netronome Systems.
"Our performance and configurability requirements were achievable with Denali's flexible DFI-compliant DDR2/3 controller, DDR2/3 PHY and PCIe 2.0 solutions".
Further reading
Software takes on SoC register management
New software boosts SoC design efficiency by automating the generation and management of the vast numbers of on-chip control registers in complex chip designs.
Memory controller IP supports encounter synthesis
Cadence Design Systems has announced support for Cadence Encounter RTL Compiler global synthesis on Databahn memory controller products.
"These subsystem components are important ingredients in our high-performance 65nm Flow processor which provides unsurpassed L2-L7 processing capability for our customers".
The Databahn portfolio provides a comprehensive infrastructure for configuring, analysing, and generating optimal controllers for any given application interface.
The Databahn combination DDR3/DDR2 memory controllers and hardened PHY products achieve speeds up to 1600Mbit/s.
Together they offer a powerful multiport solution with configurable features and functionality to satisfy system performance requirements, significantly reducing integration and interoperability risks.
The Network Flow Processor (NFP) family is highly flexible and programmable with a high-performance parallel processing architecture for processing complex Layer 2-7 algorithms, deep packet inspection, encryption, PKI hardware acceleration, traffic management and forwarding at wire speed.
The NFP multicore architecture combines 40 multithreaded microengines, each with eight threads per microengine, optimised for packet processing.
"High-quality IP is essential to solving DDR2/3 memory system requirements and for incorporating PCIe 2.0 technology, especially when dealing with sophisticated and high-throughput applications", says Brian Gardner, Vice President of IP Products for Denali.
"With our design IP products, which include support for the latest DDR2/3 and PCIe 2.0 specifications, we are providing customers with flexible, high-performance controller IP, reducing their design risks, and enabling seamless integration into their system environment".
"We also realise the importance of providing a complete IP solution that helps to ensure that Netronome will be able to meet aggressive schedules for their designs and we are pleased to be working with Netronome to achieve this".
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