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News Release from: Design Automation Conference
Edited by the Electronicstalk Editorial
Team on 18 March 2003
Hands-on tutorials feature again at DAC
The Design Automation Conference has revealed the lineup for this year's hands-on tutorials, a key element of the conference's diverse programme.
The Design Automation Conference (DAC) has revealed the lineup for this year's hands-on tutorials, a key element of the conference's diverse programme With an emphasis on signal and power analysis, these tutorials presented by various DAC exhibitors will be in-depth, interactive sessions that allow attendees to solve specific design challenges through guided hands-on experience using the latest tools and methodologies
This article was originally published on Electronicstalk on 8 Nov 2004 at 8.00am (UK)
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DAC will be held from 2nd to 6th June 2003, at the Anaheim Convention Centre.
"There's no better way to learn and understand the latest technology and tools than through actual hands-on experience", said Ellen M Sentovich, 40th DAC Tutorial Chair and research scientist at Cadence Berkeley Labs.
"Because of their overwhelming popularity last year, we have decided to make the hands-on tutorials an ongoing part of our programme so that delegates may have the opportunity to experience various aspects of chip design in an interactive manner".
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The topic for this years hands-on tutorials will be "Signal and power integrity analysis and methodology".
The tutorials will address a wide breadth of power analysis and reduction challenges, from power distribution networks in multi-million-gate ICs to signal integrity at multigigabit speeds.
Other issues to be discussed include, gliching, coupling, noise and electromigration.
Each tutorial will focus on a specific design challenge and encourage attendees to work with the tools, hands-on and in real time.
Each three-hour tutorial will be limited to the first 30 to enrol, with a cost of $50 per tutorial.
Student-to-workstation ratios will be 2:1.
The seven selected tutorials will take place between Monday 2nd June and Thursday 5th June, and include: "What is all this noise about signal and power integrity?", hosted by Sequence Design; "Signal and power integrity analysis and methodology", from Cadence Design Systems, IOTA Technology and Synplicity; "Power and signal integrity simulation of PCBs and packages", with Sigrity; "Ensuring signal and power integrity at nanometer technologies", with Magma Design Automation; "3.125Gbit/s with your hair on fire: simulation-based signal integrity analysis of digital interconnects at multi-gigabit speeds", with Xilinx and Mentor Graphics Corp; "Full-chip dynamic power grid methodology from planning to verification", with Apache Design Solutions; and "Signal and power integrity validation with in-circuit measurements", with NPTest.
More information and registration details are available from the DAC website.
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