Product category:
Design and Development Software
News Release from: Direct Insight | Subject: TimingDesigner
Edited by the Electronicstalk Editorial
Team on 18 November 2005
Timing analysis speeds data interface
design
Chronology has expanded its TimingDesigner interactive timing analysis and timing diagram product to include tighter integration with vendor-specific board design and FPGA flows.
Chronology has expanded its TimingDesigner interactive timing analysis and timing diagram product to include tighter integration with vendor-specific board design and FPGA flows TimingDesigner version 8.0 is available immediately and also includes new timing diagram functions aimed to increase productivity, along with new usability enhancements tailored for datasheet creation and revision
This article was originally published on Electronicstalk on 4 Mar 2005 at 8.00am (UK)
Related stories
ARM board hosts embedded Linux development
Direct Insight has begun shipments of a comprehensive embedded Linux development kit based on the Atmel AT91RM9200 microcontroller with ARM920T core.
Support package aids mobile graphics development
Sophia Systems has released its Gold board support package based on Microsoft Windows CE 5.0 for Sandgate II development platforms running the Intel PXA270 processor and 2700G multimedia accelerator.
"Engineers designing high-speed devices and boards are continuously presented with new timing challenges", said Hania Younis, General Manager of Chronology.
"Chronology has enhanced TimingDesigner 8.0 to increase accuracy and expedite FPGA and board design flows, while expanding its timing diagram functionality and improving usability to further streamline high-speed data interface design".
Chronology has teamed up with Altera to increase accuracy and expedite the FPGA design process by allowing users to better manage the timing challenges inherent with high-speed design.
Further reading
Reference design enables VoIP development
The Sandgate II-P is a VoIP reference design/enabling platform developed by Sophia Systems based on Intel PXA270 applications processor.
Development tools support latest XScale processor
New development tool solution sets support Intel's newest processor family (codenamed Monahans) based on third generation Intel XScale architecture.
Upgrade for real-time Windows extension
Microsoft Embedded partner Direct Insight is now shipping an enhanced version of the market-leading real-time extension for Windows.
Chronology's TimingDesigner now works closely with Altera's Quartus II, providing a smooth hand-off of critical timing data between high-density FPGAs and board-level designs, so users can identify and resolve timing issues and validate that timing constraints have been met.
The new features include: hand-off of timing analysis results are used as constraints to drive Quartus II place and route to increase timing accuracy; and post-route timing information from Quartus II is imported by TimingDesigner, allowing validation and visual confirmation of critical internal FPGA signal timing relationships.
"Altera's Quartus II software enables the fastest path to design completion for high-density FPGA design", said Jim Smith, Altera's Director of EDA Relations.
"By enabling users to quickly identify and address timing closure issues between FPGAs and other board-level components, the new integration with Quartus II and TimingDesigner will allow Altera customers to achieve even greater productivity".
TimingDesigner 8.0 also provides enhanced interfaces for board-level designers using Cadence Design Systems' OrCAD Capture and Allegro PCB design tools.
Users can import EDIF files from OrCAD Capture to automate the creation of design components and ports for new projects within TimingDesigner, resulting in substantial time savings.
In addition, TimingDesigner 8.0 offers a seamless way to import net propagation delay information from Allegro PCB design tools, allowing users to increase the accuracy of their post-route net delay analysis results and identify unexpected timing closure issues.
TimingDesigner 8.0 brings a number of new timing diagram functions and usability features to increase productivity and streamline high-speed data interface design.
Designs with high-speed data interfaces typically include multiple representations of differentially ended signals.
With TimingDesigner 8.0, users can save significant design time by simply selecting a button to designate any signal, derived signal, clock, or derived clock as a differential signal for any given diagram.
TimingDesigner 8.0 also offers new clock enable and output enable equations for derived signals, simplifying the creation of selectively clocked functions and tristate buffer representations.
In TimingDesigner 8.0, Chronology also introduces several new usability features tailored for datasheet creation and revision.
It has a unique capability to provide visual context for cause and effect events, where users can define a relationship between source and target edges with a curved arrow of selected line width and colour.
Additionally, a new active break feature lets users collapse time periods at selected locations within a diagram while compensating all measurements if break events are crossed.
The new nominal value support allows designers to perform analysis with nominal or average values in addition to existing min/max values, enhancing options for datasheet creation and maintenance.
TimingDesigner 8.0 is available now.
Chronology offers several licensing options, including perpetual and time-based.
Pricing starts at Eur 2240 (GBP 1775) depending on the configuration.
TimingDesigner is supported on the Microsoft Windows, Sun Solaris, HP-UX and Linux platforms.
Chronology products are available in the UK from Direct Insight, the company's exclusive UK distributor since 1992. Request a free brochure from Direct Insight ...
• Direct Insight: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
