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Product category: CompactPCI Boards and Assemblies
News Release from: Dynamic Engineering | Subject: CPCI2PMC
Edited by the Electronicstalk Editorial Team on 04 September 2006

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The cPCI2PMC (cPCI to PMC) adapter/carrier convertor card provides the ability to install a PMC card into a standard cPCI slot.

The cPCI2PMC (cPCI to PMC) adapter/carrier convertor card provides the ability to install a PMC card into a standard cPCI slot The cPCI2PMC has a PMC card slot mounted to a universal 3U 4HP cPCI card, and is suitable for 32/64 with 33/66MHz bus operation

The PMC user I/O connector Pn4 is optionally connected to J2 for rear panel I/O.

The PMC bezel connector is mounted though the cPCI mounting bracket.

The cPCI bus is buffered with 10ohm series resistors.

The PCI clock is distributed with a zero delay buffer.

The cPCI2PMC design is passive with no added delays to access the PMC hardware.

The traces are carefully routed with proper attention paid to the impedance and reference planes to maximise compatibility with the cPCI system.

The passive design of the cPCI2PMC reduces system latency.

The PCI bus is interconnected to the PMC via 64bit 66MHz capable layout.

The slower and narrower device will determine the interface characteristics.

The M66EN jumper allows the user to specify the PCI speed capabilities.

M66EN is interconnected between the cPCI bus, jumper, and PMC device.

The PCI VIO is interconnected to the PMC directly.

The PCI backplane will determine the bus voltage reference.

The voltage select pins are not installed on the cPCI2PMC and it is left to the user to properly select the PMC and cPCI motherboard for cPCI voltage level considerations.

Many PMCs are "universal" and can work with 3.3 or 5V cPCI backplanes.

If you need to use a 3.3V card on a 5V backplane or vice-versa please consider the cPCIBPMC3U64 design.

The bridge implementation provides level shifting between the cPCI and PMC buses.

The cPCI2PMC follows the PMC specs for maximum power consumption and heat dissipation (7.5W).

The power is routed from the cPCI to PMC connectors with mini-planes each of which is rated for more than the maximum PMC draw.

The individual pins on the JN4 (PN4) connector are accessible when the I/O option is specified.

With cPCI J2 has two definitions - in a 64bit PCI implementation J2 has the upper A/D and control signals and in a 32 bit PCI implementation J2 has the rear panel I/O.

With resistor jumpers the I/O or the PCI signals can be connected to J2.

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