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News Release from: DVCon
Edited by the Electronicstalk Editorial
Team on 31 August 2006
Conference calls up design and
verification papers
The 2007 Design and Verification Conference is now accepting paper, panel and tutorial submissions.
The 2007 Design and Verification Conference (DVCon), sponsored by Accellera, is now accepting paper, panel and tutorial submissions Proposals that reflect real experiences using hardware design and verification languages, advanced tools and methodologies are encouraged
This article was originally published on Electronicstalk on 8 Nov 2004 at 8.00am (UK)
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DVCon will be held from 21st to 23rd February 2007 at the DoubleTree Hotel in San Jose, California.
It is the premier conference focusing on the application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits.
The conference will focus on the use of specialised design and verification languages such as Verilog, SystemVerilog, VHDL, PSL SystemC, e and Vera, as well as general purpose languages such as C and C++.
All paper, tutorial and panel submissions related to using HDLs, HVLs or other languages used for hardware design or verification will be considered.
Paper and panel proposals are due by 19th September 2006.
Proposals are also being accepted for special sessions and sponsored tutorials.
Special sessions may consist of embedded tutorials of one to two hours in length or may be focused on a specific topic with a list of invited papers/presentations relevant to that topic.
A limited number of sponsored tutorials will be also available.
Proposals must be submitted by 5th October 2006.
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