Structured ASICs are ready to roll in 2005

eASIC Corp has successfully tested and characterised the first Structured eASIC family member, the FA600.

eASIC Corp has successfully tested and characterised the first Structured eASIC family member, the FA600.

The test chips, fabricated by a European IDM partner on a 0.13-micron process, were used to test functionality and characterise timing and power for the Structured eASIC device.

The FA600 is the smallest member of the company's Structured eASIC product family.

Structured eASIC products feature an innovative combination of FPGA-like flexibility and ASIC-like performance in a unique offering of NRE-free ASIC.

The complete product family is scheduled for production release in Q1 2005.

"We are extremely pleased with the success of this most important milestone in the release of the Structured eASIC offering", said Zvi Or-Bach, eASIC President and CEO.

"The Structured eASIC product family is aimed at reviving ASIC design through maskless customisation; hence NRE-free structured ASIC".

"eASIC's unique technology closes the growing NRE gap between ASIC product revenue and ASIC development cost".

"This paradigm shift has been very well received by the engineering community, and we are grateful to the many engineers who cast their vote to rank eASIC the number-one logic and programmable logic ultimate product, as reported in the EE Times Ultimate Product Survey".

"Our technology has been validated by world class OEMs and is being used for embedded configurable platforms, and we are now ready to deliver the first NRE-free structured ASIC".

eASIC has developed a unique structured ASIC technology called Structured eASIC.

The patented Structured eASIC architecture consists of an array of logic cells (eCells) with SRAM based LUTs (lookup tables) and flip-flops.

eCells are interconnected by a segmented wiring grid using upper metal layers, which are customised per customer design with a single Via-mask.

Logic programming of the eCell is done similarly to an FPGA, by loading a bit-stream to program the LUTs and flip-flops after powering up the device.

Thus, a customer design is implemented on the Structured eASIC fabric by using a combination of bit-stream to program the LUTs and single custom via-mask for customising the routing.

Moreover, single via-customisation is a perfect fit for direct-write e-beam lithography.

Using direct-write e-beam completely eliminates the customisation tooling cost, shortens time-to-market, and adds manufacturing flexibility, allowing eASIC to provide the industry with an NRE-free customised ASIC device.

The FA600 device is the smallest of the four members of the Structured eASIC product family, ranging from 600,000 to 3 million gates, and featuring embedded memory from 0.4 to 1.6Mbit, programmable I/Os, PLLs and embedded microprocessor (8051).

Supporting standard CAE tools or tailored Magma design flow, this product family is scheduled for release in Q1 2005.

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