Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: eASIC Corp
Edited by the Electronicstalk Editorial
Team on 28 February 2005
Configurable logic on the shortlist
eASIC's configurable logic product, eASICore, has been selected as an ACE (Annual Creativity in Electronics) Awards finalist by CMP Media's EE Times.
eASIC's configurable logic product, eASICore, has been selected as an ACE (Annual Creativity in Electronics) Awards finalist by CMP Media's EE Times Based on its innovative technology and usability advantages, the eASICore was nominated for Ultimate Product of the Year in the category of Logic and Programmable Logic
This article was originally published on Electronicstalk on 9 Jun 2004 at 8.00am (UK)
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In this ACE Awards programme, EE Times will recognise the people, companies and products that demonstrated leadership in the electronics industry.
The review committee for the ACE Awards is composed of the leading lights of academia, industry visionaries and Wall Street's top executives.
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Further reading
Structured ASICs top the poll
The Structured eASIC has been named as the "Number-one ultimate product" in the logic and programmable logic category of a study held by EE Times and eeProductCenter.
Structured ASICs are ready to roll in 2005
eASIC Corp has successfully tested and characterised the first Structured eASIC family member, the FA600.
"We are delighted that leading technologists and executives in our industry have chosen eASIC's product as an ACE Award finalist", said Zvi Or-Bach, eASIC Founder and CEO.
"This is in recognition of our breakthrough configurable logic technology that is providing a viable and affordable custom logic design methodology and product".
The current methodologies for design and manufacture of customisable logic are not only suboptimal but they are no longer viable in many cases.
Both standard cell and FPGA have hit the wall at deep submicron.
This opens the window of opportunity for new and innovative configurable logic technologies.
History has shown that when current ways of doing things are broken then innovation prevails and a new era starts.
This new era will reverse the trend of declining ASIC starts and will once more allow cost effective logic customisation eASIC has a unique configurable logic technology implemented in its structured eASIC products.
The patented architecture consists of SRAM-based logic cells and flip-flops that are interconnected by a segmented wiring grid utilising upper metal layers.
The logic cells programming is done similarly to an FPGA, by loading a bit-stream to program the LUTs (look-up-tables) and initialise the flip-flops after powering up the device.
The routing and interconnection is performed similar to other ASICs, but uses just a single via-layer for customisation.
Thus, a customer design is implemented on the Structured eASIC fabric by using a combination of bit-stream to program the LUTs and a single custom via-mask for customising the routing.
Moreover, the single mask can be eliminated for prototyping and low-volume by using direct-write e-beam.
Hence, eASIC's use of maskless lithography removes the customisation tooling cost, shortens time-to-market, and adds manufacturing flexibility, allowing eASIC to provide the industry with an NRE-free customised ASIC devices with densities, power and performance akin to a standard cell ASIC.
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