Amba Platform IP runs on structured ASICs

eASIC Corp has announced the availability of ARM Amba Platform IP (PIP-Amba) from Cast for eASIC's 90nm Nextreme structured ASIC product family.

eASIC Corp has announced the availability of ARM Amba Platform IP (PIP-Amba) from Cast for eASIC's 90nm Nextreme structured ASIC product family.

Cast, which joined the company's newly established eZ-IP Alliance programme, will partner with eASIC to provide customers with the essential IP cores and software infrastructure for eASIC's soft ARM926EJ microprocessor core.

The PIP-Amba package will enable designers to successfully and rapidly build complete embedded systems using the industry standard ARM926EJ processor in a configurable logic fabric.

The unique combination of the ARM926EJ core, the Cast PIP-Amba and the Nextreme logic fabric enables designers to build cost-optimised custom embedded systems in a zero mask charge and no minimum order quantity.

"We're extremely pleased to be a charter partner in eASIC's eZ-IP Alliance program, and we see big benefits for our new common customers", said Hal Barbour, President of Cast.

"The combination of our PIP-Amba 'SoC kernel' with the ARM926EJ processor now provides one of the quickest, least-expensive ways to develop custom embedded systems".

"By partnering with ARM, Cast, and other leading IP core providers, eASIC aims at helping its customers gain competitive advantage, leveraging the combined benefits of reusable cores with low-power and low-cost structured ASICs", commented Jasbinder Bhoot, Senior Director of Marketing at eASIC.

"Cast, who has been providing high quality IP cores for cell-based ASIC and FPGA vendors for many years, understands the benefits and limitations of these technologies and can now broaden its customer reach by including Structured ASICs".

"We welcome CAST to our eZ-IP Alliance and we look forward to working together to answer customer needs that are currently not being addressed by those vendors".

The PIP-Amba package includes an AHB, an AHB Arbiter, an APB Bridge, a watchdog timer, two timers, a Scalable Interrupt Controller, two 16550 UARTs with FIFOs, general purpose I/O (GPIO), an internal SRAM, an external bus interface and a SDRAM controller.

It includes the multi-master and arbitration features of the high-performance AHB bus, and a bridge to the slower APB peripherals bus.

The architecture makes it straightforward to add additional IP cores or custom logic to either bus.

The PIP-Amba includes everything required for successful implementation: HDL RTL source code for the included cores; essential software, including boot code and device drivers; sophisticated HDL testbench, including external models and interfaces; simulation script, vectors, expected results, and comparison utility; synthesis script; and comprehensive user documentation, including detailed specifications and a system integration guide.

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