Structured ASICs add PCIe and DDR2 interfaces

Two new high-speed interfaces are available for eASIC's 90nm Nextreme structured ASIC family: a PCI Express (PCIe) endpoint controller and a DDR2 memory controller.

eASIC Corp and ASIC Architect have announced the immediate availability of two new high-speed interfaces for eASIC's 90nm Nextreme structured ASIC family: a PCI Express (PCIe) endpoint controller and a DDR2 memory controller.

The PCIe controller features maximum data throughput with a latency of less than 11 clock cycles and provides local connectivity for, wireless, desktop, enterprise and communications system platforms.

The DDR2 core is tuned to provide connectivity to the latest DDR2 memories at speeds up to 533MHz.

Both PCI Express and DDR2 Controllers have been hardware proven in eASIC's Nextreme structured ASICs devices.

As a new member of eASIC's eZ-IP Alliance, ASIC Architect will collaborate with eASIC to port its world-class high speed interface IP library to Nextreme structured ASICs in order to provide system designers with the advantages of low unit cost, no mask charges and fast turnaround.

"Customers are always looking for cost-effective silicon-proven solutions without compromising on performance, latency and gate count", said Purna Mohanty, Vice President of ASIC Architect.

"Implementing the high-performance cores from ASIC Architect on Nextreme Structured ASICs provides proven platform for fastest time to market for our mutual customers".

"ASIC Architect brings a wealth of experience in developing high performance interfaces for multiple applications", said Jasbinder Bhoot, Senior Director of Marketing at eASIC Corp.

"In addition to broadening the eASIC IP portfolio, ASIC Architect contributes expertise and support to ensure customers get to market quickly".

"By partnering with leading IP providers, eASIC reinforces its goal to provide the electronic design community with an efficient alternative to existing FPGA and ASIC solutions through a disruptive technology".

The PCIe x4 endpoint controller core is the first to be implemented on eASIC's Nextreme structured ASICs.

It is part of a portfolio of ASIC Architect PCIe options that are available in multiple application interface datapaths (32, 64, 128bit) and multiple lane configurations (x1, x2, x4, x8, x16).

The application interface of these cores can be optionally integrated with Amba 3 AXI Bridge Core from ASIC Architect to connect to the Amba 3 AXI bus.

The DDR2 controller core in 64bit configuration with ECC is the first to be implemented on eASIC's Nextreme structured ASICs.

The DDR2 controller core comes with configurable memory datapath widths (16, 32, 64bit) with optional ECC support.

The architecture of the product defines a very low latency and high throughput of the core.

The application interface of the core can be optionally integrated with Amba 3 AXI bridge core from ASIC Architect to connect to the Amba 3 AXI bus.

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