Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: eASIC Corp
Edited by the Electronicstalk Editorial
Team on 15 February 2007
German and French channel partners for
eASIC
EASIC has announced two new channel partners in Europe for its Structured ASIC devices, namely Chipeo from France and Si-Bahn from Germany.
eASIC has announced two new channel partners in Europe for its Structured ASIC devices, namely Chipeo from France and Si-Bahn from Germany Under the agreement, these European channel partners will provide the 90nm Nextreme Structured ASIC devices, along with local design and sales support, to a growing community of configurable logic users
This article was originally published on Electronicstalk on 9 Jun 2004 at 8.00am (UK)
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"Chipeo and Si-Bahn were chosen for their expertise and experience in providing dedicated customer service and superior technical support to FPGA and ASIC customers", says Massimo Verita, eASIC Vice President of Customer Engineering.
"eASIC works closely with its channel partners to maximise success for both the partner and the customer, by co-operating to provide cost-effective solutions and best-in-class service in a timely manner".
"We recognised an increasing interest from European prospects who are seeking alternatives to existing FPGA and ASIC solutions".
"With the help from our new channel partners we can expand our reach and extend the local support in France and Germany, providing the electronic-design community with the advantages of our Nextreme Structured ASICs, including low cost, no mask charges, and fast turnaround of any volume required"".
"We are very pleased to be part of the eASIC channel partnership program", says Jean-Francois Lambert, Managing Director of Chipeo in France.
"This partnership will allow us to assist and provide our customers with a cost-effective ARM-based Structured ASIC solution for communication, networking and emerging markets".
Jean-Luc Couturier General Manager of Si-Bahn , in Germany said: "We are very pleased to represent eASIC because we are now able to offer to our customers the cheapest and fastest design flow, from the IP Cores implementation directly to the eASIC chips".
"With neither NRE charges, nor minimum order quantity, customers are able to verify their designs on silicon within a few weeks and move on to production right away".
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