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Product category: Recruitment, Reports and Resources
News Release from: EEMBC
Edited by the Electronicstalk Editorial Team on 21 February 2007

Benchmarks to compare multicore
implementations

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New benchmarks will address multiprocessing systems, multicore processors and multithreaded processors.

The Embedded Microprocessor Benchmark Consortium is to roll out new benchmarks that will address multiprocessing systems, multicore processors and multithreaded processors The EEMBC effort, which has been underway since mid-2006, is being led by John Goodacre of ARM, who serves as Chair of EEMBC's Multiprocessing Workgroup

With the proliferation of multicore processor implementations, the need is growing for performance benchmarks that can give an accurate indication of the value of transitioning from a single core to a multicore system, in addition to determining the impact of system-level bottlenecks, such as those encountered when moving data on and off a multicore chip.

EEMBC is addressing this challenge with new multicore benchmark suites that will enable a standardised evaluation of the benefits of concurrency while providing the scalability needed to support any number of multiple cores.

EEMBC's multicore benchmark software will initially support symmetrical multicore processors with shared memory and will use a thread-based API to establish a common programming model.

The benchmarks will target three forms of concurrency, including task decomposition, multiple data stream processing, and the processing of multiple workloads.

Task decomposition allows multiple threads to co-operate on achieving a unified goal and demonstrates a processor's support for fine grain parallelism.

Processing of multiple data streams uses common code running over multiple threads and demonstrates how well a solution can scale over scalable data inputs.

Finally, multiple workload processing shows the scalability of a solution for general-purpose processing and activates concurrency over both code and data.

To implement this strategy on the benchmark level, EEMBC is developing a test harness that will communicate with the benchmark through an abstraction layer that is analogueous to an algorithm wrapper.

This test harness will provide a flexible interface to allow a wide variety of thread-enabled workloads to be tested.

"These exciting new benchmarks will show how efficiently multicore processors are able to execute multiple contexts in parallel", said Shay Gal-On, Director of Software Engineering at EEMBC.

"They will thus help drive the development of processors with parallel resources for the embedded market segment, while providing an unbiased method for allowing system developers to compare competing processors".

In addition to using some of the existing EEMBC benchmarks in its multicore-enabled benchmark suites, EEMBC has begun work on multicore-capable VoIP and H.264 benchmarks.

Nonmember companies are encouraged to join the consortium now to participate in the final definition and testing stages.

EEMBC's multicore-enabled benchmarks will be available for licensing in 2007.

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