Product category:
Design and Development Software
News Release from: EDA Solutions | Subject: T-Spice
Edited by the Electronicstalk Editorial
Team on 08 March 2007
Analogue simulator handles larger
volumes of data
New tool suite will feature a 3D RF extraction tool that uses a field solver technique to calculate interconnect parasitics in three dimensions.
Tanner EDA will unveil a multithreaded version of its Spice analogue simulator T-Spice at DATE 2007 Its suite of analogue and mixed-signal integrated circuit and MEMS design tools is designed to run under Microsoft's new Vista operating system which spans schematic capture (S-Edit), simulation (T-Spice), layout (L-Edit) and foundry compatible design verification (HiPer Verify)
This article was originally published on Electronicstalk on 15 Oct 2003 at 8.00am (UK)
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The new analogue simulator will not only offer higher performance than its single-threaded counterpart but will also be able to handle larger volumes of data when running under Microsoft Vista.
For example, transient simulations are an average of 40% faster on dual-CPU machine than on a machine with a single CPU.
The new tool suite will feature a 3D RF extraction tool that uses a field solver technique to calculate interconnect parasitics in three dimensions.
The tool performs fast, hierarchical extraction of devices and interconnect, with 2D resistance and 3D capacitance extraction, resulting in a standard Spice netlist.
An integrated routing capability for chip assembly and analogue layout will be introduced at the show.
The router works with the current schematic driven layout (SDL) module of L-Edit and will include the ability to route up to 1000 blocks of arbitrary shape.
The new router is an area router designed to automate the job of routing noncritical analogue signals or doing full chip assembly when connecting up your analogue and digital blocks.
Finally, Tanner will be demonstrating its first multi-threaded simulation of the T-Spice simulation tool.
This will enable T-Spice to use multiple processors when solving the large matrices during simulation, with potential time saving of up to 60%.
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