Chip layout tool adds 3D RC extraction

Tool reduces design errors and shortens the design verification process, particularly for deep submicron technologies where interconnect delays start to play a dominant role.

Tanner EDA has added hierarchical 3D resistance and capacitance (RC) extraction capabilities to its L-Edit chip layout tool for analogue and mixed-signal design.

The new tool, HiPer-PX, was demonstrated for the first time at DATE 2007.

It provides high performance, accurate modelling of parasitics occurring both across metal layers and between the metal layers and the chip substrate.

HiPer-PX can also extract the device substrate resistance, which can have an effect on crosstalk at the submicron level.

The tool reduces design errors and shortens the design verification process, particularly for deep submicron technologies where interconnect delays start to play a dominant role and second-order effects such as cross coupling become significant.

HiPer-PX is fully integrated within L-Edit, ensuring ease of use and minimising training time.

Like L-Edit, the extraction tool represents a very cost-effective alternative to similar tools from the larger EDA vendors.

The extraction process is based on proven and very accurate field solver technology.

The tool extracts the resistance and capacitance of interconnects and devices, highlighting any potential crosstalk and timing delays in the design.

Both 2D and 3D electromagnetic field analysis techniques accurately and efficiently extract RC values from the layout and detailed simulation in Spice determines time delays and signal integrity effects.

The extraction tool quickly determines problem nets based on criteria that are critical to design performance and provides batch mode processing for easily checking multiple blocks.

The L-Edit layout editor has an intuitive interface which increases drawing speed through the use of object snapping, one-click horizontal or vertical alignment, and base points.

The tool can perform complex Boolean and derived layer operations with arbitrary polygonal curves and shapes and it uses external GDSII cell libraries for a smooth design flow.

Its compact code runs easily on laptop PCs.

HiPer-PX starts at US $21,495 per seat and will be available in Q4 2007.

Existing L-Edit users will be able to add this capability for $15,995.

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