MCU core is smaller and faster than original 8051

The T8051 microcontroller core is targeted at IC designers who want to make use of complete 8bit architecture functionality while substantially reducing the size of their systems.

Available now from Evatronix, the T8051 IP core is claimed to be the world's smallest microcontroller to implement Intel 8051 instruction set architecture.

Thanks to its considerable size reduction and efficient management of available resources the design has one of the best performance-to-size ratios on the market.

With the CPU's 2700 gates, the T8051 is targeted at IC designers who want to make use of complete 8bit architecture functionality while substantially reducing the size of their systems.

This lowest possible gate count is especially valuable for engineers working with mixed-signal designs implemented in older processes with larger feature sizes, where the silicon area is a significant factor.

The T8051 makes it possible to replace hard-coded control FSM with a programmable microcontroller - a task which was previously hindered by the significant difference in gate count between the two solutions.

Now that this IP core raises the bar for the minimal implementation size of this famous microcontroller's architecture, its versatility and ability for configuration make it an obvious choice.

Despite its tiny size, the T8051 is a powerful 8bit microcontroller.

Instruction cycle latency has been tuned to minimise hardware resources; however, the core still performs 4.1x better than the original Intel 8051 in terms of Dhrystone MIPS per megahertz.

Communication with both built-in and external memories has been accelerated by demultiplexing the address and databuses, and alternative port functions such as external interrupts and serial interface are available on separate pins - all this to give the user a possibility to connect and effectively manage a greater number of peripheral devices.

The T8051 also features a complete Evatronix Application-debugging Support Environment (EASE) that enables users to control the microcontroller directly in target applications.

It consists of the Evatronix Debug Interface (EDI), which is a software plug-in for the Keil development environment, Evatronix Debug Pod (EDP) for an easy IP core-to-PC connection via the USB port and a built-in on-chip debug support (OCDS) module implemented directly in the core itself.

However, the OCDS can be removed for the final implementation to fit the T8051 into yet smaller space.

"The feedback we received from over 100 companies that licensed our 8051-compliant IP cores to design more than 200 chips showed there us a niche for an ultra-small, yet configurable version of this microcontroller", says Wojciech Sakowski, Evatronix President.

"Many companies have been able to design an 8051-compliant IP, but achieving this goal with such a low number of gates and more than quadruple performance gain over the original Intel device gives us a significant competitive advantage".

"We believe our customers will find this combination particularly beneficial for a large class of their designs".

The T8051 IP core is available for licensing now.

Standard deliverables include various sets of scripts for trouble-free synthesis and simulation as well as an extensive Verilog 2001 testbench, while the proprietary prototyping environment can be purchased as an option.

Evatronix design team is ready to share its extensive expertise in developing this highly successful IP cores family and assist customers in adapting the microcontroller to their particular applications.

Back to top