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News Release from: Elixent | Subject: DFA1000
Edited by the Electronicstalk Editorial
Team on 04 April 2002
Reconfigurable processors optimise DSP
tasks
Elixent has released the DFA1000 family of accelerators for use with standard RISC processors running DSP algorithms.
Elixent has released the DFA1000 family of accelerators, for use with standard RISC processors running DSP algorithms Designed to deliver at least an order of magnitude improvement in performance over current leading DSPs, this is the first implementation of D-Fabrix, Elixent's reconfigurable signal processing (RSP) technology
This article was originally published on Electronicstalk on 16 Oct 2002 at 8.00am (UK)
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The DFA1000 family is accompanied by a complete suite of support tools, making it easy to integrate into a standard design flow and directly benefiting designers of both RISC processor systems and SoCs.
Elixent was launched in July 2001 to exploit a technology, D-Fabrix, that offers unprecedented performance and the ability to dynamically reconfigure to allow silicon reuse.
As the first product based on that technology, the DFA1000 family of accelerators have a highly scalable nature, low power and small die area.
Further reading
Reconfigurable toolflow enhances productivity
Elixent has announced a major upgrade of D-Sign, the development toolflow for the company's patented reconfigurable algorithm processing (RAP) technology, D-Fabrix.
Architecture cuts signal processing real estate
Elixent unveiled details of its next generation D-Fabrix reconfigurable algorithm processing (RAP) architecture this week at In-Stat's Spring Processor Forum in San Jose, California.
Development platform has educational aims
The EmbestUniversity is a teaching platform focused on embedded system development.
This makes them suitable for many applications, from wireless communications to high-volume consumer products.
Each DFA1000 accelerator is delivered as a hard macro, a format that offers many advantages.
Hard macros are ready-validated, eliminating many of the risks and unknowns in developing an SoC, while the time to port to a new silicon process, a traditional concern with hard macros, is eliminated by the small number of leaf cells.
This makes a port to a new process extremely easy.
"Reconfigurable signal processing promises to bridge the gap between dedicated ASICs and programmable DSPs by offering better price/performance at low power by providing more optimal processing of a wide range of algorithms", said Will Strauss of market research firm Forward Concepts.
"A thorough and robust toolchain will be the key to the success of this technology and Elixent is on track to deliver on this requirement and their recent announcements with Celoxica and Interra indicate that they are addressing ease of use as well".
A DFA1000 accelerator maps directly to a standard RISC via the AHB system bus and has its own dedicated I/O ports that can be used for the high-bandwidth/low-latency interfaces required in multimedia and communications systems.
As the footprint of the macro is parameterisable, it can be easily varied to fit the space available.
This enables the accelerator to be scaled to meet both performance and area requirements.
Even a small array provides significant DSP acceleration, while a larger one offers the very high performance needed by the most demanding tasks.
For example, FIR filters can be built with sampling rates of greater than 100MHz and an 8 x 8 DCT (a major building block of JPEG and MPEG video compression systems) achieves greater than 100Mpixel/s performance despite being implemented using only a couple of hundred ALUs.
No programmable DSP processor currently available can achieve this.
The DFA1000 family is supported with an extensive programming toolset, providing several options for design entry.
Because reconfigurable signal processing is a new design technique, many hardware and software engineers are starting to learn the skill.
Elixent has anticipated this by providing each group with a familiar programming interface.
For hardware engineers, designs can be entered as if the DFA1000 accelerator was a simple FPGA.
The design is described in industry-standard Verilog, and synthesised down onto the array.
Each design operates like a "virtual hardware accelerator" - a familiar concept for hardware engineers.
For software engineers, Celoxica provides the DK1 tool.
This allows the accelerator to be programmed from C, providing extensive benefits in time to market and productivity and releasing the benefits of reconfigurable signal processing to millions of C programmers.
Both tools feed into the DFA1000 family's standard toolflow at a high level.
The interface from the design entry tools into the back end of the toolflow is well defined, allowing third party suppliers to offer additional design entry options in the future.
Regardless of the programming style used, once the program is written and downloaded, the DFA1000 functions as a dedicated hardware accelerator, eliminating real-time conflicts, multiple operating systems and other issues that can cause problems.
Removal of these challenges alone provides a significant boost in engineering productivity.
There are five members of the DFA1000 family; DFA1000-128, DFA1000-256, DFA1000-512, DFA1000-1024 and DFA1000-2048, containing; 128, 256, 512, 1024 or 2048 ALU arrays, respectively.
The first products will be commercially available in Q2 2002.
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