Product category:
Intellectual Property Cores
News Release from: Elixent
Edited by the Electronicstalk Editorial
Team on 26 August 2002
Alliance to link Matlab with
reconfigurable DSP
AccelChip and Elixent are to provide a direct path from Matlab to D-Fabrix, Elixent's reconfigurable algorithm processor (RAP) architecture.
AccelChip and Elixent are to provide a direct path from Matlab to D-Fabrix, Elixent's reconfigurable algorithm processor (RAP) architecture The two companies are developing a version of AccelChip's behavioural synthesis tool, AccelFPGA, to produce optimised implementations of DSP algorithms targeting Elixent 's D-Fabrix embedded RAP array
This article was originally published on Electronicstalk on 4 Apr 2002 at 8.00am (UK)
Related stories
Reconfigurable processors optimise DSP tasks
Elixent has released the DFA1000 family of accelerators for use with standard RISC processors running DSP algorithms.
Reconfigurable algorithm processing stars in Japan
Elixent's first public demonstration of its reconfigurable algorithm processing (RAP) technology took place last week at the CEATEC show in Japan.
By implementing AccelFPGA in the D-Fabrix tool chain, Elixent can help reduce its customers'design cycles by several man-months through the automatic generation of RTL models and simulation testbenches.
This technique also eliminates many risks associated with ambiguous written specifications that can cause unforeseen design iterations late in the design process "The performance requirements of today's communication technologies are driving DSP designers to seek hardware accelerated solutions to replace their traditional DSP processors that can no longer provide the throughput required", commented Dan Ganousis, President and CEO of AccelChip.
"Elixent's D-Fabrix architecture is an ideal solution to this performance gap and we feel Elixent is well poised to be very successful in the communications, consumer, transportation and defence industries".
Further reading
Reconfigurable processors to feature at SoC show
Elixent will demonstrate its patented reconfigurable algorithm processing technology, D-Fabrix, at the 1st International SoC conference in California on 19th and 20th April.
Reconfigurable toolflow enhances productivity
Elixent has announced a major upgrade of D-Sign, the development toolflow for the company's patented reconfigurable algorithm processing (RAP) technology, D-Fabrix.
Elixent has purchased AccelFPGA for internal use in the design and development of D-Fabrix intellectual property (IP) and DSP core cells, and has licensed a custom version of it to be included in the tool chain provided to its customers.
The tool enables a true top-down DSP design process by providing a direct link from Matlab models and Simulink system-level designs to standard RTL design flows based on the Verilog and VHDL design languages.
This efficient design path allows Elixent 's customers to do all their DSP algorithm development in the Matlab language and then quickly realise the hardware implementation in the company's D-Fabrix architecture This tight link of the Matlab and D-Fabrix design flows will allow customers to reduce time-to-market, optimise performance and cost, and eliminate design iterations late in the product development cycle "By including AccelChip 's behavioural synthesis tool in the D-Fabrix tool chain, we can address our customer 's requirement to support their existing design environment", said Kenn Lamb, Elixent's CEO.
"Matlab is the dominant design language for DSP algorithm development and with AccelFPGA we can now provide seamless integration with our RTL-based tool chain".
Elixent 's patented RAP technology allows developers to exploit parallelism to achieve high-performance by using the reconfigurable hardware architecture of the D-Fabrix RAP array.
In traditional DSP processors, the architecture is fixed and developers have to fit their algorithms to the architecture, thus sacrificing performance and functionality.
With D-Fabrix IP, developers can fit the architecture to their algorithms to deliver the required performance at the most cost effective price and shortest time-to-market.
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