Reconfigurable toolflow enhances productivity

Elixent has announced a major upgrade of D-Sign, the development toolflow for the company's patented reconfigurable algorithm processing (RAP) technology, D-Fabrix.

Elixent has announced a major upgrade of D-Sign, the development toolflow for the company's patented reconfigurable algorithm processing (RAP) technology, D-Fabrix.

D-Sign v1.4 offers greatly enhanced tool performance, including a four-fold improvement in both synthesis times and in placement speed.

These significantly increase the productivity of engineers working with the technology, reducing development and design time.

Full support for VHDL and for v1.2 of the D-Fabrix architecture is also included.

D-Sign v1.4 features new 'place and route' technology which improves the utilisation of the D-Fabrix architecture.

By improving the mapping of an application on to the array, gains of up to 20% are achieved in both speed and utilisation.

This is another step towards Elixent's ultimate target of matching ASIC density with a programmable technology.

Additionally, the toolflow's open interfaces have been enhanced, giving Elixent's partners (including Celoxica and AccelChip) improved access to the design flow and more efficiently supporting their next generation of improved tools.

D-Sign v1.4 now offers support for v1.2 of the D-Fabrix architecture.

This upgrade enables users to automatically take advantage of the power-saving features of the architecture, such as improved clock gating (which allows parts of the array that are unused in an application to be turned off) and power-down/standby modes.

Standby mode reduces power consumption to typically 1/1000 of that of an FPGA.

The VHDL support in D-Sign v1.4 has been extended to include the full synthesisable subset of the IEEE1076-2002 definition of the language.

This is in response to demand from customers working on large programs and is in addition to the tool's existing comprehensive implementation of IEEE 1364.1 Verilog.

"While Verilog is the tool of choice for our Far Eastern customers designing low cost consumer applications, VHDL remains popular in the European market and in defence applications," said Andy Elms, VP of customer engineering.

"Also, many of our customers are currently using the flow for large designs, therefore the improved speed and efficiency of the upgrade will be of significant benefit to them." D-Sign v1.4 was released to customers at the end of June.

All current customers will be upgraded under maintenance.

Elixent has a programme of continuous extensive enhancement of the toolflow and D-Fabrix architecture.

D-Fabrix provides the world's lowest power reprogrammable solution for implementing algorithm processing in SoC devices, providing ASIC designers with a production-ready flexible alternative to fixed function chips.

The technology uses reconfigurable arrays of arithmetic elements which enable algorithm functionality to be added or changed post-fabrication, enabling bugs to be fixed or even the whole chip to be customised and reused in a new application.

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