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News Release from: Faraday Technology | Subject: UMC 65nm LL memory compiler
Edited by the Electronicstalk Editorial
Team on 01 February 2008
Technology meets 65nm challenges
Faraday Technology's UMC 65nm LL allows users to generate memory options including words, bits and aspect ratios, while retaining the desired area, performance and power specification.
Faraday Technology has released the UMC 65nm LL memory compiler The use of 65nm technology provides good memory density
This article was originally published on Electronicstalk on 2 Feb 2007 at 8.00am (UK)
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Faraday expands commitment to ARM-based CPUs
Faraday Technology has licensed the ARM926EJ-S microprocessor and the ARMv5TEJ instruction set for its next-generation FA CPU family for embedded, networking and multimedia applications.
However, due to process variation and higher design complexity, memory leakage, yield loss and wiring congestion become major concerns and big challenges for designers.
Faraday's 65nm memory compiler addresses these challenges.
Hsin Wang, Vice President of Sales at Faraday said "It enables our customers to be competitive on the market with lower power consumption, smaller size and higher level of integration".
Faraday's 65nm memory compiler uses UMC's low leakage process.
It allows users to generate memory options including words, bits and aspect ratios, while retaining the desired area, performance and power specification.
The memory compiler provides features for design-for-manufacturing (DFM), as well as built-in two-row redundancy and a programmable sensing margin.
To facilitate chip-level integration, an optional BIST test interface (BTI) is provided for better routability, which will also reduce overall chip size by eliminating the use of a memory routing channel.
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