Technology meets 65nm challenges

Edited by the Electronicstalk editorial team Feb 1, 2008

Faraday Technology's UMC 65nm LL allows users to generate memory options including words, bits and aspect ratios, while retaining the desired area, performance and power specification.

Faraday Technology has released the UMC 65nm LL memory compiler.

The use of 65nm technology provides good memory density.

However, due to process variation and higher design complexity, memory leakage, yield loss and wiring congestion become major concerns and big challenges for designers.

Faraday's 65nm memory compiler addresses these challenges.

Hsin Wang, Vice President of Sales at Faraday said "It enables our customers to be competitive on the market with lower power consumption, smaller size and higher level of integration".

Faraday's 65nm memory compiler uses UMC's low leakage process.

It allows users to generate memory options including words, bits and aspect ratios, while retaining the desired area, performance and power specification.

The memory compiler provides features for design-for-manufacturing (DFM), as well as built-in two-row redundancy and a programmable sensing margin.

To facilitate chip-level integration, an optional BIST test interface (BTI) is provided for better routability, which will also reduce overall chip size by eliminating the use of a memory routing channel.