Product category:
Memory Devices and Modules
News Release from: Fairchild Semiconductor | Subject: SSTV16859
Edited by the Electronicstalk Editorial
Team on 28 February 2001
Dual-output buffer for DDR SDRAM modules
Fairchild Semiconductor has introduced a dual-output registered buffer for 184-pin, 2.5V PC200/PC266, 72bit-wide registered double data rate (DDR) SDRAM modules.
Fairchild Semiconductor has introduced a dual-output registered buffer to add to its complete DDR DIMM support solution for 184-pin, 2.5V PC200/PC266, 72bit-wide registered double data rate (DDR) SDRAM modules Fairchild is the only company that currently offers a full interface solution for these DDR DIMMs with the following devices: the FMS7857 phase locked loop (PLL) clock driver; the FM34W02 serial presence detect EEPROM, SSTV16857 and the new dual output SSTV16859
This article was originally published on Electronicstalk on 14 Mar 2001 at 8.00am (UK)
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This solution is fully compliant to the JEDEC DDR SDRAM Registered DIMM Design Specification.
The newest addition to this interface solution is the sstv16859 dual output registered buffer.
It is a 13bit register used for address and control buffering designed for use with 184-pin and 232 DDR-1 high-density (stacked) memory modules.
The device features a differential input clock, SSTL-2 compatible data inputs and has a LVCMOS compatible RESET input.
It has been fabricated on an advanced sub-micron CMOS process using the industry standard 64-pin TSSOP and is designed to operate at power supplies of 2.5V.
Fairchild is also currently the only company to offer a full interface solution for PC133 SDRAM memory modules.
This solution comprises the FMS72509 and FMS72510 PLL clock drivers; the 74VCXF162835, 74VCX162838, and 74VCX162839 registered buffers; and the FM34W02 serial presence detect EEPROM.
This solution is intended for use in 168-pin, 3.3V, 133MHz registered SDRAM DIMMs.
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