PLL clock drivers target high-speed clocking

Two low voltage PLL clock drivers designed for use in high-speed memory clocking applications are now available from Fairchild Semiconductor.

Two low voltage PLL clock drivers designed for use in high-speed memory clocking applications are now available from Fairchild Semiconductor.

Operating at speeds up to 175MHz, these parts are designed for high clock fanout and where matching requirements for skew and jitter are critical.

Applications include registered DIMM memory modules and wherever common clock timing is critical in system clock distribution.

The FMS7950 and FMS7951 are direct replacements for the Motorola MPC950 and MPC951.

The FMS7950 operates off a crystal or oscillator input with clock multiplier; the FMS7951 accepts a PECL clock input and features zero delay and clock multiplication capability.

Both parts provide nine configurable CMOS outputs with less than 250ps of output-to-output skew and less than 300ps of cycle-to-cycle jitter.

The FMS7950 and FMS7951 are each packaged in a 32-lead LQFP and rated for 0 to 70C operation.

VDD range is 3.0 to 3.6V.

A power down pin is provided for system testing.

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