Product category:
Design and Development Software
News Release from: Fairchild Semiconductor | Subject: EnSigna Lab
Edited by the Electronicstalk Editorial
Team on 05 October 2001
Free online simulation tool for LVDS
designs
Fairchild Semiconductor has launched a free online simulation tool that supports system architects designing with LVDS technology.
Fairchild Semiconductor has launched a free online simulation tool that supports system architects designing with LVDS technology Working with Innoveda, Fairchild now offers an online, interactive point-to-point simulator for modelling, evaluation and testing of LVDS integrated circuits
This article was originally published on Electronicstalk on 30 Jan 2002 at 8.00am (UK)
Related stories
Modelling methodology improves interface accuracy
Fairchild Semiconductor's EnSigna Lab modelling experts have developed an improved IBIS model generation methodology for its LVDS interface IC portfolio.
Dual-output buffer for DDR SDRAM modules
Fairchild Semiconductor has introduced a dual-output registered buffer for 184-pin, 2.5V PC200/PC266, 72bit-wide registered double data rate (DDR) SDRAM modules.
Bus hold makes logic more predictable
Fairchild Semiconductor has made a number of additions to its LCX family, the logic industry standard for 3.3V applications.
Since its announcement in October 2000, Fairchild's EnSigna Lab has supported systems designers with component selection, device modelling, system simulation and performance evaluation for multidrop and multipoint backplanes using high-performance ICs such at GTLP.
Now EnSigna Lab offers the same services for point-to-point architectures that use differential and single-ended I/O.
The LVDS simulation tool is powered by XTK from Innoveda.
XTK is the industry's leading signal-integrity analysis and crosstalk simulation tool, designed to help solve signal integrity problems on single printed circuit boards and multiboard systems.
On the EnSigna Web, selection of the point-to-point simulator invokes an interactive session in which a system configuration and I/O device are chosen.
Environments include PC traces, connector and cable configurations and backplane traces.
Cable, connector and PC trace characteristics can be chosen and modified to optimise signal integrity or analyse performance boundaries.
Designers can evaluate across frequency and cable or trace length.
Stimuli include clock and psuedo random bit sequence (PRBSs) allowing for evaluation and configurability and IC outputs including eye diagrams and single event output waveforms.
"In design definition, the need for accurate simulation is a critical component to narrow the time between new product introductions, while retaining quality and decreasing costs", said Innoveda's vice president of marketing, Rick Almeida.
"The complexity of today's systems demands stringent simulation and verification testing".
Fully equipped with the most advanced test and data-acquisition equipment, EnSigna Lab uses sophisticated simulation software for complex backplane and subsystem environments, and is staffed with industry experts in the optimisation of throughput and signal integrity for advanced applications.
The services available through EnSigna Web are free of charge and accessible 7 days a week, 24 hours a day.
• Fairchild Semiconductor: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
