Product category:
Intellectual Property Cores
News Release from: Gaisler Research
Edited by the Electronicstalk Editorial
Team on 22 February 2007
Simulator to support IP cores
Gaisler Research has begun working with Aldec, a pioneer in mixed language verification and advanced debugging tools for FPGA and ASIC devices.
Gaisler Research has begun working with Aldec, a pioneer in mixed language verification and advanced debugging tools for FPGA and ASIC devices The GRLIB IP core library from Gaisler Research is ideally suited for SoC designs and implements plug and play capabilities that minimise the engineering effort during the design phase
This article was originally published on Electronicstalk on 13 Sep 2005 at 8.00am (UK)
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The partnership will ensure that Aldec's Active-HDL and Riviera simulator users can readily download and simulate a large set of very advanced and mature IP cores.
"We are pleased to be working with Aldec and look forward to a successful partnership to increase the number of IP cores that are supported by their simulator tools, and at the same time ensure that our IP cores are truly portable between design environments", stated Per Danielsson, CEO of Gaisler Research.
"Aldec and Gaisler Research engineering teams are working together to ensure that the GRLIB IP core library is compatible with the Active-HDL and Riviera mixed language simulators".
"The latest GRLIB release already includes support for these tools on Windows and Linux platforms", added Sandi Habinc, Senior Vice President of Engineering, Gaisler Research.
"Gaisler Research has been constantly delivering advanced and demanding IP cores, our co-operation will ensure compatibility while our tools evolve and their cores become more complex", stated David Rinehart, Vice President of Aldec.
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