Product category:
Intellectual Property Cores
News Release from: GDA Technologies | Subject: GRIO IP
Edited by the Electronicstalk Editorial
Team on 29 April 2004
Silicon IP cores support RapidIO specs
A new range of IP cores are fully compliant with both serial and parallel RapidIO specifications and are targeted for embedded, communications and networking applications.
A new range of IP cores are fully compliant with both serial and parallel RapidIO specifications and are targeted for embedded, communications and networking applications The GRIO (GDA RapidIO controller IP cores) solution is derived from the RapidIO technology-based controller design licensed from Freescale Semiconductor, a wholly owned subsidiary of Motorola
This article was originally published on Electronicstalk on 8 Sep 2003 at 8.00am (UK)
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GRIO IP is packaged as a highly configurable, reusable design and marketed worldwide by GDA as the GRIO RapidIO IP family.
GDA has also joined the RapidIO Trade Association and will become an active member of the association in accelerating its global deployment.
"RapidIO interconnect architecture provides best-in-class features in performance, scalability and reliability, which are fundamental requirements for connectivity in high-speed applications.
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Our GRIO IP cores provide a set of features and capabilities that will foster new generations of innovative products based on RapidIO technology", said Prakash Bare, Vice President of IP Business at GDA.
"We look forward to working with the RapidIO Trade Association to make the RapidIO fabric one of the compelling technology choices for backplane, board, mezzanine, and device interconnectivity".
"The RapidIO Trade Association is delighted that GDA Technologies is introducing its RapidIO IP cores to the market", said Sam Fuller, President of the RapidIO Trade Association.
"Customers are demanding RapidIO-based solutions for their next-generation embedded systems and proven IP offerings like GDA Technologies' GRIO IP core will find a large and ready market".
The RapidIO interconnect architecture, designed to be compatible with the most popular integrated communications processors, host processors, and networking digital signal processors, is a high-performance, packet-switched, interconnect technology.
It addresses the high-performance embedded industry's need for reliability, increased bandwidth, and faster bus speeds in an intra-system interconnect.
The RapidIO interconnect allows chip-to-chip and board-to-board communications at performance levels scaling to 10Gbit/s and beyond.
The GRIO IP cores adhere to the latest RapidIO specifications and are available for both ASIC and FPGA implementations.
The cores are designed for reuse, and their flexible backend interfaces enable easy integration into wide range of applications.
GRIO's configurable and modular architecture is optimised for latency, reliability, and small silicon footprint and is independent of application logic, PHY designs, and target technologies.
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