Software smoothes transition to test

STIL Verifier is a product aimed at automating the transition between verification and test.

Globetech Solutions has announced the availability of STIL Verifier, a product aimed at automating the transition between verification and test.

Based on the IEEE1450 Standard Test Interface Language (STIL) standard, STIL Verifier can produce or validate complete test programs, allowing engineers to automate tedious and error prone transitions to and from automated test equipment (ATE) environments.

STIL Verifier comprises two flows: STIL Simulate parses, validates and imports STIL programs into simulation-based verification environments.

STIL Capture records and exports complete verification scenarios, trivialising functional test program generation and speeding up silicon debug flows.

STIL Verifier interfaces to popular IEEE standard verification languages such as e and SystemVerilog, allowing for early incorporation of STIL in the design process and co-verification of STIL with RTL, design netlists and embedded test structures.

"Testability is a key DFM challenge facing the entire semiconductor ecosystem", said Stylianos Diamantidis, Managing Director and CTO of Globetech Solutions.

"STIL Verifier makes working with STIL faster and easier, facilitating collaboration between test and verification experts and contributing directly to reduced time-to-volume".

STIL Verifier is currently available for e environments.

SystemVerilog support will be available later in Q4 2006.

Back to top