Product category:
ATE Systems
News Release from: Goepel Electronic | Subject: Boundary scan for Digitaltest in-circuit testers
Edited by the Electronicstalk Editorial
Team on 06 October 2005
In-circuit testers integrate boundary
scan
Goepel Electronic has developed a next generation boundary scan option for Digitaltest MTS 180, MTS 300 and MTS 888 series in-circuit testers.
Goepel Electronic has developed a next generation boundary scan option for Digitaltest MTS 180, MTS 300 and MTS 888 series in-circuit testers The solution is based on a complete integration of the recently launched Scanflex hardware architecture in combination with Cascon Galaxy boundary scan system software, and also involves the ICT digital pin electronics
This article was originally published on Electronicstalk on 26 Jul 2004 at 8.00am (UK)
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"Now we meet the customer requirements of a perfect combination of Goepel Electronic's JTAG/boundary scan and Digitaltest ICT".
"The result of the development co-operation is a completely integrated solution with interaction of the test resources of both systems", says Bettina Becker, Marketing and International Sales Manager for Goepel Electronic.
"In particular, the direct control of the ICT pin electronics by the boundary scan environment has the advantage of each nail acting as additional virtual scan pin in a boundary scan test".
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"Applying our philosophy of 'extended boundary scan', the user now is able to dramatically increase the test coverage".
In terms of hardware, the integration is based on the extremely high-performance Scanflex PCI controller models SFX/PCI1149-x with programmable TCK frequencies up to 20MHz (A type) and 50MHz (B type), respectively.
The connection to the UUT is realised using a Scanflex transceiver model SFX-TAP4/C, which provides four programmable TAP for the optimal adaptation to the UUT.
The UUT is contacted by means of the standard interface of the ICT.
Additional electronics is not necessary.
Furthermore, 32 dynamic I/O are available on the Scanflex hardware.
In terms of software, the complete Cascon Galaxy development and execution environment was integrated into the CITE operating system by Digitaltest via the comfortable CAPI interface (Cascon application programming interface).
Thus, all Cascon software editions can run on the ICT.
The ICT pin electronics' control is managed with the Hyscan technology implemented in Cascon Galaxy.
Hyscan enables the synchronisation of serial JTAG/boundary scan test vectors with parallel test vectors through a special emulation process.
The parallel vectors are linked to the physical I/O interface at run time, providing tester hardware independence.
The manual or automated generation of test vectors, the debugging, and the fault diagnostic is executed by the native JTAG/boundary scan tools, whereby each ICT channel acts as a bidirectional boundary scan pin at the contacted net, completely transparent to the user.
The first systems will be delivered in the fourth quarter of 2005.
Further integration solutions are already under development, including the Digitaltest Condor MTS 500 flying prober. Request a free brochure from Goepel Electronic ...
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