Boundary scan module meets DIMM interface

Edited by the Electronicstalk editorial team Jul 31, 2007

Low-cost digital I/O module enables the testing of all signal and voltage supply pins of JEDEC compliant DIMM168 plug connectors.

The latest addition to the Cion product family from Goepel Electronic, the Cion Module/DIMM168 is a low-cost digital I/O module that is serially controlled via TAP by special Cion ASIC chips, and enables the testing of all signal and voltage supply pins of JEDEC compliant DIMM168 plug connectors.

"The new module for testing DIMM168 sockets is another step towards the consistent availability of our innovative Cion Module architecture for all important interfaces", explains Thomas Wenzel, Managing Director of Goepel Electronic's Boundary Scan Division.

"At the same time, we're meeting the demands of many customers for an extensive product portfolio of test solutions in the lower price segment".

The Cion Module/DIMM168 is plugged into a respective socket, whereby the interface stages' voltage between 1.8 and 5V are adapted automatically.

Because the modules are equipped with transparent TAP, several boards of the same or different types can be cascaded in a daisychain configuration.

The structural boundary scan test of all DIMM168 signal and voltage supply pins are executed by the onboard Cion ASIC ICs.

All channels can be independently switched as input/output/tristate.

To ensure protection of test equipment and unit under test (UUT), Cion Module/DIMM168 provides special safety mechanisms such as "Unstress" to prevent damages in case of shorts, extended power yield and voltage programmable TAP.

These features guarantee not only a high reliability and flexibility but also outstanding safety and extendibility.

The new hardware module is completely supported by all JTAG/boundary scan controllers of the ScanBooster and Scanflex families as well the integrated boundary scan software platform System Cascon.

Users can easily integrate the Cion Module/DIMM168 into a test project with fully automatically generated test vectors.

Any faults can be interactively debugged and visualised graphically at pin and net level in the layout and schematic.