I/O modules check out memory interfaces

Low-cost digital module enables the testing of all signal and voltage supply pins of JEDEC-compliant DDR2 Mini DIMM 244 sockets.

New from Goepel Electronic, the Module/DIMM244so is the latest addition to the company's CION family of I/O modules.

The new low-cost digital module is serially controlled via TAP by special CION ASIC chips, and enables the testing of all signal and voltage supply pins of JEDEC (JESD79-2C) compliant DDR2 Mini DIMM 244 sockets.

"The opportunity to test DDR2 Mini DIMM 244 interfaces was on the top of our customer's wish list", says Raj Puri, Vice President Marketing and Sales for Goepel Electronics.

"These new CION modules provide a cost effective solution for applications in laptops, PCs and workstations".

The CION Module/DIMM244so is plugged directly into the sockets to be tested, whereby the voltage adaptation of the interface steps is done automatically.

Because the modules are equipped with transparent TAP, several boards of the same or different types can be cascaded in a daisychain configuration.

The structural boundary scan test of all DIMM 244 signal and voltage supply pins are executed by the onboard CION ASIC ICs.

All channels can be independently switched as input/output/tristate.

To ensure protection of test equipment and unit under test (UUT), CION Module/DIMM244so provides special safety mechanisms such as "unstress" to prevent damages in case of shorts, extended power yield and voltage programmable TAP.

These features guarantee not only high reliability and flexibility but also outstanding safety and extendibility.

The new hardware module is completely supported by all JTAG/boundary scan controllers of the ScanBooster and Scanflex families as well the integrated boundary scan software platform System Cascon.

Users can easily integrate the CION Module/DIMM244so into a test project with fully automatically generated test vectors.

Any faults can be interactively debugged and visualised graphically at pin and net level in the layout and schematic.

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