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News Release from: HD Lab | Subject: SystemC behavioural synthesis style guide
Edited by the Electronicstalk Editorial
Team on 23 July 2007
Style guide sets standard for SystemC
design
Reference book documents production-proven expertise and design techniques based on SystemC, the de facto standard for ESL design and verification.
HD Lab has published its "SystemC behavioural synthesis style guide", a reference book that documents production-proven expertise and design techniques based on SystemC, the de facto standard for ESL design and verification HD Lab has been actively engaged in SystemC design, verification and design methodology consulting for the past three years
This article was originally published on Electronicstalk on 16 Jan 2006 at 8.00am (UK)
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Based on its experience with real world client projects, HD Lab has accumulated and cultivated various design techniques and best practices using SystemC.
The design style guide documents these design techniques and expertise in a well organised, easily implementable manner.
The guide has been used by consultants at HD Lab, and proven at number of client design project sites in leading systems and semiconductor companies throughout Japan.
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As compared with traditional RTL-based design methods, the SystemC design methodology described can yield significant savings in overall design cycle time anywhere from one third to a half.
The guide includes examples of design blocks in excess of 3 million gates being designed using SystemC descriptions.
The guide also follows and implements JEITA SystemC working group's proposal on behavioural synthesis guidelines.
To achieve wider acceptance of behavioural synthesis, the style guide is written with a variety of design engineers in mind.
The style guide methodically defines and explains SystemC descriptions that will produce high quality circuits.
To assist in the adoption of behavioural synthesis, the style guide includes a rich set of coding examples as well as building methodologies for a verification environment.
The coding examples and templates described in the style guide will also be available for download, to further accelerate the first-time adoption of SystemC design techniques.
The style guide first introduces a SystemC based design and verification methodology, and explains the benefits of using SystemC.
Secondly, it explains the uniform coding rules for design reuse within the company and between different companies.
It follows the organisation and conventions of the popular "RTL design style guide" (the de facto RTL coding guideline published by STARC and HD Lab).
The guide presents circuit architecture, verification strategy and design methodology in a thorough and easy to follow style for both designers and design managers.
It presents key coding techniques in a systematic fashion to allow an expedited learning curve.
The initial learning curve savings can be as great as 50%.
And it provides detailed behavioural synthesis examples following descriptions defined by Forte Design Systems Cynthesiser, the most popular and widely accepted SystemC synthesis tool, which is in production use in more than 25 of the top systems and semiconductor companies.
Cynthesiser automatically generates high-quality hardware designs from SystemC.
The guide also provides behavioural synthesis design examples, coding templates and sample codes for download from HD Lab's web page (for no incremental cost).
Regular updates to the style guide are planned as new versions of tools in synthesis and verification becomes available.
HD Lab is also actively participating in the JEITA (Japan Electronics and Information Technology Industries Association) SystemC task group.
HD Lab will be actively seeking to encourage world-wide acceptance of the "SystemC behavioural synthesis design style guide" through its planned release of an English version in 2008.
"With the availability of the design style guide, new ESL design style will be widely accepted", says HD Lab's Founder/CTO, Hiroyasu Hasegawa.
"As a result, productivity gains along with design reuse will accelerate".
"Furthermore, the style guide will enable novice and beginning level design engineers to easily become productive in SystemC based design".
"With plentiful free examples and code samples, learning SystemC will be much more streamlined".
"We have observed a large number of Japanese customers achieve dramatic productivity gains by successfully adopting SystemC-based design", says Brett Cline Vice President of Marketing and Sales at Forte Design Systems.
"HD Lab's design style guide will allow companies around the world to leverage this combined experience and quickly adopt SystemC design and synthesis to shorten their overall design cycle".
Takeshi Hasegawa, Chairing JEITA EDA Technical Committee's SystemC Working Group comments: "Unlike RTL synthesis, there are no standard coding style for SystemC synthesis".
"There were lots of trial-and-error types of approaches".
"We are pleased to see that JEITA's working group's input has been implemented by HD Lab in this guidebook".
Hasegawa, who is also Director of the ESL and Verification Department at Fujitsu, adds: "Since key elements of design environment building and knowhow for design are organised and available in the design style guide, cost savings to a design team is tremendous".
"We expect this new methodology to be the key productivity differentiator".
The design style guide will be available in Japan from 31st July 2007.
A single corporate license will be JPY 4 million per set (approximately US $33,000).
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