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Product category: Design and Development Software
News Release from: HDL Works | Subject: Ease 5.2
Edited by the Electronicstalk Editorial Team on 09 September 2004

Environment manages mixed language
design

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HDL Works describes Ease 5.2 as the ideal design entry environment for VHDL, Verilog and mixed language designs for FPGA and ASIC design.

HDL Works describes Ease 5.2 as the ideal design entry environment for VHDL, Verilog and mixed language designs for FPGA and ASIC design Synthesis and simulation tool independency enables users to select their favourite tools while setting up a complete design flow

Ease continues to be the most intuitive design entry environment in the market, while offering all necessary features for both advanced and novice HDL designers.

Many improvements have been made in this new version.

These changes include: Tcl driven version management with support for ClearCase, RCS and Synchronicity Design Sync; Verilog 2001 support; and a new project browser.

Today's designs are getting more complex and larger, and so designers need tools that enable them to build and manage these designs as if they were simple and small.

Ease simplifies the coding and debugging stage of the flow and enables design groups to quickly produce state of the art design code which is easy to overlook and maintain.

Ease offers the best of both worlds with the user's choice of graphical or text based HDL entry, while automatically generating optimised HDL code in either VHDL or Verilog.

Industry standard version control environments deal with design and configuration management enabling multiple users to work simultaneously on the same Ease project.

Ease is designed to improve productivity and communication in design teams.

Ease 5.2 is now available.

Prices begin at US $4000.

An evaluation copy can be downloaded from the HDL Works website.

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