Software optimises the edit-compile-debug cycle

HDL Works has released a new version of Ease, the graphical HDL design entry environment.

HDL Works has released version 6.0 of Ease, the graphical HDL design entry environment.

Ease is known for its ease of use and fast editing capabilities for any VHDL, Verilog or mixed language ASIC or FPGA design.

Synthesis and simulation tool interfaces are built-in, optimising the user's edit-compile-debug cycle.

Next to many smaller improvements in performance and ease of use, major new features are focused on: HTML generation; HDLWare parameterisable logic functions; close integration with Actel's Actgen, Altera's MegaWizard and Xilinx' CoreGen; and IP usage.

HTML generation for any HDL design is performed in seconds, providing the user with an HTML description of all relevant project data.

The HTML version of the project can be used to browse through the design hierarchy, view all objects and colour coded source code.

This greatly enhances quick generation of detailed documentation for any HDL design and allows you to share design information using an intranet or the internet.

External IP (including company legacy code and vendor libraries from Actel, Altera, Xilinx and others) can now be easily specified, and symbol libraries for these IP modules are generated on the fly.

Ease is billed as the most intuitive graphical HDL design entry tool in the industry, providing the user with a better means of communication, documentation and design entry and modification for any HDL design targeted for FPGA or ASIC.

It includes integration with industry standard revision control systems for real multi-user support.

Ease 6.0 is now available.

Prices begin at US $4200.

Ease can be downloaded for a free ten day evaluation from the company's website.

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