Product category:
Design and Development Software
News Release from: Hier Design
Edited by the Electronicstalk Editorial
Team on 18 March 2003
Newcomer set to shake up FPGA design
market
Hier Design is an EDA industry newcomer intent on delivering software for high-speed, high-complexity FGPA designs.
Hier Design is an electronic design automation (EDA) industry newcomer intent on delivering software for high-speed, high-complexity FGPA designs - a market it claims has been overlooked by traditional EDA suppliers The company is creating the next EDA beachhead by fuelling the movement from ASICs to FPGAs and will launch software in July 2003 to enable programmable devices to obsolete ASIC technology for most standard products
This article was originally published on Electronicstalk on 5 May 2003 at 8.00am (UK)
Related stories
FPGAs gain virtual prototyping support
Hier Design is to provide full support for Xilinx's new class of 90nm Spartan field programmable gate array solutions.
Floorplanner helps FPGA designers to plan ahead
The PlanAhead hierarchical floorplanner is the heart of the new silicon virtual prototyping solution from Hier Design for high-end field programmable gate arrays (FPGAs).
"The vast majority of designers are creating boards and FPGAs, not ASICs and SoCs", observes Jackson Kreiter, Hier Design's CEO and Chairman.
"The EDA industry has traditionally ignored this mainstream design community, creating a huge market opportunity for us.
Hier Design is building a company and product line to service the needs of the sophisticated FPGA designer community in a manner that will offer productivity and profitability, the underpinnings of a successful EDA company".
Further reading
Floorplanning aids FPGA design
PlanAhead hierarchical floorplanning and analysis software from Hier Design offers full support for the latest version of the Xilinx Integrated Software Environment 6.1i (ISE).
Floorplanner gains Java-based visualisation
Hier Design is to bundle Concept Engineering's NlviewJA Widget, a Java-based visual debugging software engine, into its PlanAhead hierarchical floorplanning and analysis software.
Toshiba opts for simulation analysis solution
Toshiba Corp has adopted the FineSim hybrid simulation analysis solution into its design flow.
In recent years, FPGA design starts have shot past ASICs, largely due to their long-held, time-to-market advantage.
ASICs have become out of reach for an increasing number of product applications due to skyrocketing mask costs, prolonged time-to-manufacturing, risk of respins and inventory costs.
Roger Minear of Agere Systems, a speaker at this year's International Solid State Circuits Conference (ISSCC), revealed that mask costs alone can range from $650,000 for 30-35 layers at 130nm, with the cost jumping to $1,400,000 for 90nm.
Consequently, ASIC production volumes must be high before managers can justify their staggering expense.
Conversely, product applications for FPGAs have increased because of technology breakthroughs, such as 10-million gate density, 400MHz clock speeds, embedded platform structures and economical unit costs afforded by larger 300mm wafer sizes.
Simultaneously, the increased sophistication of FPGAs is driving the need for next-generation EDA design tools that can handle them.
EDA software has not kept pace with technological advancements in FPGA hardware.
Today's designers are largely using last-generation software, created before deep submicron technologies brought an explosion in gate count and interconnect delay dominance.
The result is longer runtimes, numerous design iterations, a loss in performance, and an increasing gap between the programmable transistors available to designers and the average number they can effectively use.
This gap undermines the primary FPGA advantage time to market.
Hier Design will formally introduce its family of silicon virtual prototyping software for FPGAs in July 2003.
Its floorplanning and analysis software will be introduced first, and the company claims it will enable: high-value, multi-million-gate designs; savings of $30,000 in labour costs per design; savings of $500 per part per design; and a time-to-market advantage.
Early versions are currently in limited, pre-beta use with select customers.
Products run on Windows, Linux, and Sun Solaris Unix-based workstations, and initially will support Xilinx devices only.
The Hier team is composed today of 15 employees in research and development, marketing, sales and customer support.
Its 640m2 corporate headquarters is located in Santa Clara, California.
In addition to Kreiter, Salil Raje serves as Chief Technology Officer and Vice President of Engineering.
Peter S Teshima is Chief Operating Officer and Chief Financial Officer.
Majid Sarrafzadeh is a technical adviser and a founder.
Brian Jackson and David Tarpley are Vice Presidents of Business Development in North America and Asia, respectively.
Hier Designs board includes: Jackson Kreiter, who serves as Chairman and is its Chief Executive Officer; Ping Chao, formerly CEO Silicon Perspectives, now Senior Vice President and General Manager of Digital IC Solutions at Cadence; J George Janac, founder and Chairman of InTime Software; Lucio Lanza of Lanza Tech Ventures; and Jonah Schnel, Managing Partner at ITU Ventures.
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