Product category:
Design and Development Software
News Release from: Hier Design | Subject: PlanAhead
Edited by the Electronicstalk Editorial
Team on 23 July 2003
Floorplanner helps FPGA designers to
plan ahead
The PlanAhead hierarchical floorplanner is the heart of the new silicon virtual prototyping solution from Hier Design for high-end field programmable gate arrays (FPGAs).
The PlanAhead hierarchical floorplanner is the heart of the new silicon virtual prototyping solution from Hier Design for high-end field programmable gate arrays (FPGAs) PlanAhead increases design performance while shortening the design cycle by providing a faster, less iterative path from logic synthesis through physical design
This article was originally published on Electronicstalk on 11 Sep 2003 at 8.00am (UK)
Related stories
Floorplanning aids FPGA design
PlanAhead hierarchical floorplanning and analysis software from Hier Design offers full support for the latest version of the Xilinx Integrated Software Environment 6.1i (ISE).
Floorplanner gains Java-based visualisation
Hier Design is to bundle Concept Engineering's NlviewJA Widget, a Java-based visual debugging software engine, into its PlanAhead hierarchical floorplanning and analysis software.
Its advanced analysis capability enables designers to more easily comprehend, modify, verify and implement their FPGAs.
"FPGAs have grown so large and complex that designers are encountering the same kinds of convergence problems that have vexed ASIC designers, obstructing or even preventing design completion", remarks Jackson Kreiter, Hier Design's Chief Executive Officer (CEO) and Chairman.
"PlanAhead meets the needs of sophisticated FPGA designers who are fuelling the trend away from ASICs".
Further reading
FPGAs gain virtual prototyping support
Hier Design is to provide full support for Xilinx's new class of 90nm Spartan field programmable gate array solutions.
Development platform has educational aims
The EmbestUniversity is a teaching platform focused on embedded system development.
IC packaging partnership proves a success
IC packaging leader Advanced Semiconductor Engineering has announced its commitment to Ansoft's HFSS, Q3D Extractor and AnsoftLinks simulation products for IC packaging design and model extraction.
The types of problems designers face when designing complex FPGAs include the inability to achieve performance requirements, unpredictable routing results, routing congestion, tightly packed designs, critical paths spanning hierarchy, or heavily constrained interconnect.
Current EDA tools force designers to fix each problem individually and then re-implement the entire flattened design.
The result is lengthy and numerous design iterations that, in turn, often lead to cost overruns, slipped schedules and missed market opportunities.
ASIC designers, however, have largely alleviated these problems through the widespread use of hierarchical floorplanning, a design step between synthesis and place and route, which reduces the number and length of design iterations.
Like its ASIC counterpart, the PlanAhead floorplanner increases performance and reduces the number of design iterations by giving designers advanced insight into the place and route process.
Designers can quickly examine multiple what-if scenarios about physical design, enabling them to identify and fix potential problems beforehand.
With PlanAhead, designers can group critical paths and modules to increase routability through connectivity analysis and utilisation control.
PlanAhead provides a hierarchical, block-based and incremental design methodology, enabling designers to change only one part of the design and leave the rest intact, shortening design iterations.
Changing smaller portions of the design also helps maintain performance requirements, since results of iterative place and route are often unpredictable, particularly when performed on flattened netlists of entire chips.
Incremental design can improve physical design time by two to four times over flat methodologies.
PlanAhead's hierarchical design planning capability includes an advanced graphical user interface (GUI) that makes it easy to use for even the most inexperienced designer.
Its intuitive display of device resources, connectivity, logical and physical hierarchy lets designers quickly visualise and fix problem areas.
They can create and manipulate physical hierarchy independently from logical hierarchy, and simultaneously plan and analyse multiple physical implementations, maximising design space exploration by more quickly identifying optimal implementations.
PlanAhead also provides manual or automatic partitioning, manual or automatic physical block sizing and placement along with clock I/O and clock region planning.
Designers can implement blocks individually and then assemble them in PlanAhead for analysis of the partial designs performance before other blocks have been completed, then make any necessary changes before proceeding.
This block-based design flow provides a teamwork-friendly environment, enabling multiple designers to divide and conquer complex FPGA designs.
It also eases the reuse and retargeting of intellectual property (IP) from one device architecture to another.
PlanAhead's design analysis capabilities include timing, connectivity, utilisation, I/Os, clock regions, and carry chains, with power and other analysis capabilities to be added in the near future.
PlanAhead offers seamless integration with the Xilinx design flow by encapsulating place and route commands directly in the GUI.
It supports block-based and area-based flows, enabling incremental design methodologies.
PlanAhead supports the Xilinx Virtex-II and Spartan3 device families.
The US list price for a one year, time-based licence is $25,000.
PlanAhead is supported on Sun Solaris 5.8, Linux 7.3 and Windows XP operating systems.
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