Product category:
Design and Development Hardware
News Release from: Hardi Electronics | Subject: HapsTrak compatible serdes daughterboard
Edited by the Electronicstalk Editorial
Team on 01 June 2007
Serdes board speeds ASIC prototyping
High speed serial transceiver daughterboard accelerates verification and prototyping of ASIC based storage and communication systems.
Hardi Electronics is answering demands for high speed interfaces for ASIC prototyping with a HapsTrak compatible serdes (high speed serial transceiver) daughterboard containing an ASIC serdes evaluation chip from LSI HapsTrak guarantees that this serdes daughterboard will be compatible with all previous and future generations of HAPS (Hardi ASIC Prototyping System) motherboards
This article was originally published on Electronicstalk on 10 Mar 2003 at 8.00am (UK)
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Increasing data transmission rates is making it more difficult to verify and prototype ASIC based storage and communication systems.
For example, prototyping serdes in an FPGA has significant limitations.
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Not only are the electrical and logical behaviours different between ASIC and FPGA serdes, but the RTL verified in the prototype also requires special attention to adapt to the functionality differences.
A more accurate alternative is to prototype using a native ASIC serdes in an evaluation chip.
The engineering teams at Hardi and LSI have worked together to develop a HapsTrak compatible serdes daughterboard hosting the LSI evaluation chip.
All high speed PCB layout issues have also been addressed.
For example, signal integrity is of paramount importance.
Detailed attention is required for the prototyping PCB and cabling designs including clean power supplies and grounding, controlled impedance transmission lines and low noise.
Crosstalk, reflections, impedance matching, and length matching are some of the layout issues that must be dealt with.
The serdes daughterboard supports PCIe + PIPE, SAS, SATA, Fibre Channel, InfiniBand and GigE.
"We are seeing more and more customers run into significant issues with high speed interfaces while prototyping", says Lars-Eric Lundgren, CEO of Hardi.
"We are thrilled to have had the opportunity to work closely with LSI to solve this problem and offer such a robust high-speed connectivity solution to our ASIC prototyping customers".
"We continually to strive to provide more value to our customers by getting them prototyping faster with more accurate ASIC functionality and this new daughter board is an extension of that goal".
Mike Casey, Director of Technical Marketing at LSI adds: "Prototype based verification is being used more frequently in our own ASSP programmes".
"Hardi's implementation of our serdes opens up a flexible prototyping environment, which we can extend to our ASIC customers".
"Having a prototype that behaves as expected in the final ASIC reduces verification risks with PHY and link layer IPs and speeds in-system electrical testing".
"Our engineering teams have co-operated on this daughter board to help our mutual customers bring better designs to market faster".
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