Product category:
Intellectual Property Cores
News Release from: Imagination Technologies | Subject: PowerVR MVDA2
Edited by the Electronicstalk Editorial
Team on 15 February 2005
Core accelerates all key video standards
The PowerVR MVDA2 IP core accelerates all key video standards across a range of applications including mobile TV and handheld multimedia.
Available now from Imagination Technologies' PowerVR Division, the PowerVR MVDA2 multistandard video decode accelerator is an IP core that accelerates all key video standards across a range of applications including mobile TV and handheld multimedia MVDA2 accelerates the decode of MPEG-2, MPEG-4, WMV8, WMV9 and H.264 video streams, at resolutions programmable up to 720 x 576, offloading inverse zig-zag, inverse discrete cosine transform (IDCT), motion compensation and deblocking, the most costly stages in video decoding, from the CPU
This article was originally published on Electronicstalk on 17 Sep 2003 at 8.00am (UK)
Related stories
DAB tuner supports 5.1 audio trial
The DRX-702ES DAB digital radio tuner from Imagination's Pure Digital division will support the upcoming trial broadcast of 5.1 audio signals to be transmitted over DAB in the central London area.
Graphics IP features on ARM development board
ARM has integrated Imagination Technologies' PowerVR MBX graphics technology in a custom development chip which forms the basis of the new ARM RealView Versatile family of hardware development boards.
The reduction in CPU load achieved is typically in excess of 80% for H.264, thereby allowing the system designer to target lower cost and lower power systems.
This is of increased importance when performing quarter-pel motion compensation as used in modern video compression standards.
Deblocking can be performed either by directly accessing the macroblocks from the decoder hardware or by fetching them from system memory which allows it to be used for general video post-processing.
The MVDA2 is available with a video decode acceleration driver which supports the acceleration of common video codecs through a single easy to use interface.
The driver is available for Linux and WinCE platforms.
The MVDA2 core is configurable at synthesis time for 32 or 64bit system bus widths.
Power requirements are optimised by sophisticated power management techniques using register-level clock gating to ensure the lowest active and standby power.
A full rate H.264 Baseline profile stream decode can be achieved with the core running at less than 50MHz (CIF resolution: 352 x 288 pixel, 30 frame/s).
SD resolution is also supported with a 100MHz clock frequency.
PowerVR MVDA2 is available as soft IP and ships with: synthesis scripts; an extensive verification test suite to ensure correct implementation of the design in a SoC; a hardware implementation guide; and a comprehensive programmer's reference manual.
• Imagination Technologies: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
