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Intellectual Property Cores
News Release from: Imagination Technologies | Subject: Meta HTP IP core
Edited by the Electronicstalk Editorial
Team on 02 November 2007
IP core offers speed boosts
The multi-threaded architecture allows the overlapped execution of multiple threads, enabling multiple applications to run concurrently on the same processor.
Imagination Technologies has released the Meta HTP multi-threaded processor IP core, extending support for operating systems (OS) and applications while providing faster speeds and new architectural enhancements The multi-threaded architecture allows the overlapped execution of multiple threads, enabling multiple time-critical, DSP-rich applications and general-purpose tasks to run concurrently on the same processor, reducing power consumption and silicon area whilst increasing throughput beyond that of traditional processors so that one Meta HTP can replace multiple high-performance RISC and DSP cores
This article was originally published on Electronicstalk on 17 Sep 2003 at 8.00am (UK)
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Meta HTP implements a longer pipeline, enabling it to achieve higher clock speeds ranging from 360MHz in 130nm to 500MHz in 90nm and up to 700MHz in 65nm process using standard cells together with high-speed SRAM macros for cache.
A longer pipeline would normally reduce benchmark performance per MHzb however Meta HTP includes additional architectural features to compensate including a return address cache and branch prediction table support.
A four-threaded Meta HTP delivers up to 1552 DMIPS in a 65nm process.
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Multithreaded core to gain new compiler
Imagination Technologies is using the CoSy compiler development system from ACE Associated Compiler Experts, as the basis of the next generation compiler for the Meta multithreaded processor core.
Meta HTP will be available with integer and DSP with optional full floating point that supports both 32bit single precision and 64bit double precision formats.
The Meta HTP processor family is code-compatible with earlier members of the Meta processor family and will also introduce Imagination's Minim 16bit instruction set, as used by Imagination's Meta MTX1 for common instructions.
This increases code density by 20-30% relative to the regular 32bit instruction set.
Code compatibility with earlier Meta processors provides a wide range of applications immediately available for audio, video, communications and other embedded SOC tasks.
Despite the advanced multi-threaded architecture of the Meta HTP, software creation follows the same development flow of a traditional processor.
Meta HTP is supported by Codescape development tools from Imagination Technologies, supporting debug features such as real-time nonintrusive trace.
SoC devices are being designed for global products that offer multi-function capability, requiring multiple high-speed data stream I/O and peripherals while meeting tough system timing, power and performance constraints.
With many competing demands on memory subsystems from multiple units including CPUs, DSPs and GPUs, a processor's potential throughput is greatly reduced by SoC memory latency.
For system management the Meta HTP processor is specifically designed for high-performance real-time operation at low clock speeds, making the best possible use of memory bandwidth and providing exceptional tolerance of system latencies.
Meta HTP's multiple hardware threads are each a virtual processor operating in a parallel/overlapped manner with no context switching overheads.
Each Meta HTP hardware thread can be RISC or DSP, and each virtual processor can run an independent OS, including Embedded Linux, Nucleus or Imagination's own MeOS RTOS, or they can run code natively.
Tony King-Smith, VP Marketing at Imagination said: "Meta HTP's scalable architecture has all the benefits of multi-processing but with less silicon resource and development complexity".
"And it is significantly lower cost than a multi-processor approach".
"Its unified architecture delivers both powerful DSP and general-purpose processing whilst the multi-threading 'hides' memory latency in SoC solutions".
Traditional processors are often stalled due to multi-cycle memory latencies or unproductive whilst performing context switches in software under control of a multitasking RTOS.
Meta HTP tolerates latency much better than other solutions.
When one thread stalls, another may execute and there is zero overhead switching between threads, so stall cycles are not wasted.
On each cycle one or more threads will execute, depending upon the resource required by each thread, maximising central ALU and memory utilisation.
Meta HTP's Superthreading allows threads to run simultaneously, provided they are not competing for the same resources, to perform more work per clock cycle.
Each Meta HTP thread's capability is 'software-configurable' and not 'hardwired', as in multi-processing, for greater flexibility.
Imagination's Automatic MIPS Allocation (AMA) technology makes threads easy to use and real-time aware when running multiple time-critical tasks.
Meta HTP is designed for low power consumption.
Superthreading allows more work per clock cycle so the SoC can run at lower clock speeds while AMA handles system load balancing to meet processing deadlines.
Fine-grain power management includes low-level clock gating, thread and resource scheduling to control clock gating operation and unused resources which are automatically 'switched off' cycle by cycle.
As a result of these features Meta HTP processors can run at a far lower frequency than other processors for the same level of processing performance.
SoCs can be made inherently more efficient by combining a real-time processor, running at 'just enough' speed, with specific co-processors for specialised tasks.
The Meta HTP Coprocessor Interface supports up to eight read and/or write interfaces to allow threads to operate synchronously with other hardware modules.
Each interface supports single-cycle synchronous 64bit data exchange.
Imagination's Meta HTP processor family also includes a broad range of audio decoders and audio enhancement algorithms.
In combination with Imagination's visual IP and communications IP core families, Meta HTP completes the range of functions required by even the most advanced multimedia SoCs.
The Meta HTP has a rich DSP feature set capable of up to four 16bit MACs/cycle, or two 32bit MACs/cycle with a VLIW-like instruction template for complex DSP operations, combining four instructions in a single cycle.
Meta HTP features four-way set associative data and instruction caches and a thread-aware MMU able to support demand page virtual memory, as required by full featured OSs and optimised for Linux.
The Meta HTP debug features can be accessed through a high-speed nonintrusive JTAG connection, requiring no debugging code to be present on the Meta HTP processor.
The PC hosted advanced Codescape Debugger can gain control of the Meta HTP core as it resets, allowing ROMless boot during code development and provides a rich set of debugging features as well as initialisation of target system memory and peripherals.
Alongside the launch of Meta HTP, Imagination has also released the latest version of its Meta ATP multi-threaded processor core, based on the Meta1 architecture.
The latest release of Meta ATP includes a series of enhancements including core code memory and real-time trace support.
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