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Product category: Design and Development Software
News Release from: IAR Systems | Subject: Visualstate 5.4 embedded design and verification
Edited by the Electronicstalk Editorial Team on 15 February 2007

Software for design and verification

IAR Systems has launched visualSTATE 5.4, the latest version of its state-machine embedded-design and verification tool with a tighter integration to IAR Embedded Workbench.

IAR Systems has launched Visualstate 5.4, the latest version of its state-machine embedded-design and verification tool with a tighter integration to IAR Embedded Workbench The advanced features of Visualstate 5.4 allow both project expenditure and implementation time to be reduced substantially

The design tool now offers an integrated and iterative workflow, from design through verification to validation and debugging on hardware.

Visualstate offers a simple formalised approach to the design phase, based on the state machine subset of UML, which is much easier to learn than full UML.

It can handle thousands of concurrent and hierarchical state machines in one design, and provides formal verification and validation functions that ensure a higher quality product reaches the market.

Visualstate automatically generates compact C/C++ source code that is 100% consistent with the design.

The integration with the IAR Embedded Workbench IDE is realized as a C-Spy plug-in that displays Visualstate design model information in the C-SPY debugging environment within IAR Embedded Workbench.

The tool suite provides either full simulation or hardware debugging of the design with meaningful, high-level visual feedback into the state machine model rather than the C-level feedback that would be provided with alternative methods.

For example, this allows the user to easily set complex breakpoints on the design level, instead of using complicated and error prone C level data breakpoints.

Version 5.4 of Visualstate gives users the benefit of increasing test phase efficiency, because the initial code quality is improved by applying formal verification and early function validation.

Using formal methods of verification, it is possible to find a number of errors and mistakes that would be virtually impossible to find by conventional means.

The formal verification tests include the detection of unreachable states; dead end states; 'live lock' states; ambiguous assignments and transitions; and unused events, transitions, variables, states and action functions.

The graphical design approach of Visualstate means that intrateam communication is improved, as is the production of meaningful and consistent documentation.

Maintenance costs are also lowered, because of simplicity of the design approach and the ease of navigation, as well as the ability to change core application logic in a very simple manner.

The new version of Visualstate forms a key component of IAR YellowSuite, the integrated tool suite for development of embedded systems.

The integration between Visualstate and IAR Embedded Workbench is available for the vast majority of 8-, 16-, and 32bit architectures supported by IAR Systems. Request a free brochure from IAR Systems ...

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