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Product category: Memory Devices and Modules
News Release from: IDT | Subject: Bank-switchable dual-port memories
Edited by the Electronicstalk Editorial Team on 19 April 2002

Bank on dual ports running up to 200MHz

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Bank-switchable dual-port memories are now available from IDT with enhanced speeds up to 200MHz in sizes up to 9Mbit.

Bank-switchable dual-port memories are now available from IDT with enhanced speeds up to 200MHz in sizes up to 9Mbit This bank-switchable dual-port family provides the highest performance and density on the market, while also supplying the higher bandwidth requirement demanded by communications architectures in the enterprise/carrier-class infrastructure market, including applications such as switches, routers, hubs and RAID controllers with data transfer rates of up to 14Gbit/s

By operating at these speeds and densities, the bank-switchable dual-port devices offer higher performance and flexibility to the system designer, while also allowing for additional data storage.

In addition to providing the industry's only 9Mbit 200MHz bank-switchable devices, IDT's new dual-ports offer 36 and 18bit devices.

The 3.3V core operating voltage provides lower power consumption, and selectable 3.3/2.5V I/O operations on each port bridge the gap between operating voltages, enabling designers to interface with families of new network processors and DSPs, as well as previous generations of these devices.

And, as the new devices share the footprint of previous generations, customers can seamlessly upgrade to the new, higher-speed products.

The high-speed bank-switchable dual-ports are organized into 64 banks within a common memory array, surrounded by multiplexing circuitry to allow each bank to be accessed by either port.

Densities from 64K x 36 (IDT70V7589) to 256K x 36 (IDT70V7519) and 128K x 18 (IDT70V7399) to 512K x 18bit (IDT70V7339) are available.

The devices are capable of supporting frequencies up to 200MHz on buses of various widths, frequencies and voltage levels.

The dual-ports feature separate, independent clocks on each port to support communication between busses running at different frequencies asynchronously to one another, even with the two ports set at different voltage levels.

The two ports on the device are able to operate simultaneously, doubling the available bandwidth.

As the dual-port consumes less board space and is based on architecture with an aggressive cost per bit, designs using dual-port products can be more space- and cost-efficient.

Shared network devices will also benefit from the parity bits that support error detection and correction.

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