Product category:
Memory Devices and Modules
News Release from: IDT | Subject: TeraSync quad/dual FIFOs
Edited by the Electronicstalk Editorial
Team on 03 April 2003
Multichannel FIFOs aid data acquisition
A new range of high-speed TeraSync quad/dual FIFO products provides two or four TeraSync FIFOs in a single package, thereby reducing board space and overall system costs.
A new range of high-speed TeraSync quad/dual FIFO products provides two or four TeraSync FIFOs in a single package, thereby reducing board space and overall system costs The TeraSync quad/dual FIFOs are available in 1.25Mbit (327K x4 or x2), 2.5Mbit (655K x4 or x2) or 5Mbit (1.25M x4 or x2) total density versions
This article was originally published on Electronicstalk on 12 Apr 2001 at 8.00am (UK)
Related stories
IDT joins Texas in crossbar low-voltage logic
IDT and Texas Instruments have entered a co-operative agreement to become alternate supply sources of 3.3V crossbar low-voltage technology (CBTLV) bus switch devices.
IP coprocessors provide flexible search width
IDT has released its first commercially available Internet protocol coprocessor product portfolio that enables up to OC-768 wire speed to support ever-increasing packet processing requirements.
Each FIFO operates independently and is capable of running at 200MHz in either single-datarate (SDR) or double-datarate (DDR) mode.
The new TeraSync quad/dual FIFOs are ideal for applications where data-stream convergence and parallel buffering of multiple data paths are required, including bandwidth-demanding communications systems, data acquisition systems and medical equipment.
With the TeraSync quad/dual FIFOs, each internal FIFO has its own discrete read and write clock, independent read and write enables, and separate status flags.
While the density of each FIFO is fixed, each of the four FIFOs can be configured independently with its own datarate (SDR at 2Gbit/s or DDR at 4Gbit/s), clock frequency and bus width.
The IDT TeraSync quad/dual FIFOs have the capability of operating their I/Os at 2.5V LVTTL, 1.5V HSTL or 1.8V eHSTL levels.
The 10bit bus offers a perfect interface to several leading A/D convertors, allowing streaming data flow from data acquisition, medical imaging and other applications.
The 10bit bus also provides the ability to tag packets or frames with 1bit signalling the start of the packet/frame, and the other signalling the end.
• IDT: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
