Product category:
Memory Devices and Modules
News Release from: IDT | Subject: SFC products
Edited by the Electronicstalk Editorial
Team on 05 November 2003
Sequential flow control for DDR SDRAM
A new sequential flow-control device family is the latest addition to the IDT portfolio of flow-control management ICs.
A new sequential flow-control (SFC) device family is the latest addition to the IDT portfolio of flow-control management ICs These new devices provide high-performance data flow management by using a seamless connection to an external double-datarate (DDR) SDRAM for storing and transferring up to 1Gbit of data in a sequential fashion
This article was originally published on Electronicstalk on 12 Apr 2001 at 8.00am (UK)
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The IDT SFC devices seamlessly handle all DDR SDRAM interactions, and can support SDRAM densities of 128 or 256Mbit for a single device, allowing up to four memory devices to be connected to each SFC device.
To meet the needs of applications requiring greater than 1Gbit of memory, the ICs can easily be configured in depth expansion mode so two or more devices can be cascaded to reach multigigabit densities.
For designers whose needs for queuing are in the 20Mbit range, the IDT SFC products offer an economical alternative, as these devices are 50% less expensive than off-the-shelf solutions.
Furthermore, each SFC device can simultaneously move data into and out of the SFC part and into and out of the external SDRAM, thus enabling increased data throughput and reduced latency, making the IDT SFC products well suited for communication and networking systems, as well as medical equipment, graphics, and test and measurement systems.
Traditionally, high-density sequential queuing of data involved the use of cumbersome and time-consuming "home-grown" semiconductor solutions including expensive ASICs or FPGAs.
Implementing an IDT SFC device enables designers to use a smaller, lower cost FPGA, thereby reducing the complexity and cost of the system implementation and shortening design time.
The architecture of the SFC devices consists of independent read and write ports with associated read and write clocks operating synchronously at up to 166MHz with 6Gbit/s throughput.
The device family includes a bus-matching feature, allowing the inputs and outputs to be configured in x36, x18 or x9 bus width (IDT72T6360) or x48, x24 or x12 bus width (IDT72T6480), depending on the device selected.
A user selectable error detection and correction (EDC) feature detects and corrects single bit errors when reading from the SDRAM.
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