Product category:
Communications ICs (Wired)
News Release from: IDT | Subject: IDT88P8344
Edited by the Electronicstalk Editorial
Team on 28 May 2004
Controller accelerates packet processing
Integrated Device Technology has expanded its portfolio of flow-control management products to include a family of packet-exchange devices.
Integrated Device Technology has expanded its portfolio of flow-control management (FCM) products to include a family of packet-exchange devices The new packet-exchange family includes the IDT88P8344, the industry's first system packet interface (SPI) exchange product that integrates switching, aggregation and rate adaptation of four lower rate SPI-3 interfaces to the higher rate SPI-4 interface in VPN firewall cards, Ethernet transport and multiservice switches
This article was originally published on Electronicstalk on 12 Apr 2001 at 8.00am (UK)
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Additionally, the logical port-mapping feature of the device creates reliable, channelised data paths between network hardware elements such as network processor units (NPUs), traffic managers, multi-gigabit framers and physical interfaces (PHYs), and switch fabric interface devices.
The SPI-3 to SPI-4 exchange product is fully compliant with industry standard interface specifications and includes enhancements such as programmable SPI-3 pause insertion and additional features that ease system design.
The IDT88P8344 SPI-3 to SPI-4 exchange device uses an innovative backpressure scheme that tolerates a large range of logical port datarates.
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In general, a lower logical port datarate results in the creation of more, shorter bursts in the transfers.
In addition, SPI-3 ingress, SPI-3 egress and SPI-4 interfaces are often configured such that they support different backpressure schemes.
In the new IDT device, these different backpressure schemes are accommodated using large but efficient buffers created from segmented memory, resulting in faster response times and lower internal latency while affording absorption of large external delays caused by data and flow control pipelines in adjacent devices such as packet-forwarding engines and PHY devices.
The buffering capabilities are used to absorb network delays and prevent loss of information that might occur as a result of flow control response times.
This backpressure scheme also helps to prevent congestion and starvation at points in the datapath, resulting in a consistently managed flow of data.
In addition, the IDT88P8344 SPI-3 to SPI-4 device offers a patent-pending technology that contains an apparatus and method for transferring data that comprise a high proportion of short bursts.
In this method, data are received on a burst-by-burst basis.
Once a burst is received, it is stored in a processing queue.
Complete bursts continue to be received so long as a processing queue can accommodate a data burst.
The complete data burst is then directed to an output and used to transmit a complete data burst to a ready target port.
This accommodates and converts burst size and other burst transfer parameters between separate SPI interfaces, as specified in the SPI standards.
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