Product category:
Communications ICs (Wired)
News Release from: IDT | Subject: IDT88K8486, IDT88K8487 and IDT88K8483
Edited by the Electronicstalk Editorial
Team on 29 October 2004
Seamless connection for SPI-4 networking
hardware
Three new system packet interface packet-exchange devices aim to solve interconnect problems in core/metro/edge-based networking markets.
Integrated Device Technology has expanded its portfolio of packet-exchange flow-control management (FCM) products to include three new system packet interface (SPI) devices that solve interconnect problems in core/metro/edge-based networking markets The family supports 10Gbit/s packet processing and offers a wide range of options for logical port density and buffering capabilities, ranging from low latency SPI-4-to-SPI-4 switching through complex flow-control designs requiring SPI-4 data overbooking and aggregation
This article was originally published on Electronicstalk on 12 Apr 2001 at 8.00am (UK)
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Incorporating three SPI-4 ports, the devices can seamlessly connect multiple network hardware elements such as network processor units (NPUs), coprocessors, traffic managers, multi-gigabit framers and physical interfaces (PHYs), and switch-fabric interface devices.
In fact, the SPI-4 packet-exchange devices represent the first family of SPI-4 devices to implement this architectural flexibility and the first series of devices that allow 16 or more logical ports of two SPI-4 interfaces to be combined in a third SPI-4.
Each device within the family is targeted at a specific application.
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The IDT88K8486 is ideal for simple data switching and aggregation in applications where less than 16 channels, fast backpressure response and adequate buffers in the attached SPI-4 devices are available.
The IDT88K8487 is ideal for connecting two 24-port 10/100/1000 Ethernet MACs to a single SPI-4 NPU.
For more demanding flow-control applications, the IDT88K8483 is available for designs requiring additional buffering and packet processing due to traffic consisting of "jumbo" Ethernet frames.
With the largest amount of internal memory in the product family, it is well suited for connection to devices that have a slow backpressure response due to long internal pipelines tending to create numerous "in-flight" packets.
The entire SPI-4 product family provides many options and flexibility for demanding applications.
It doesn't penalise customers who do not require the high logical port counts or large data buffers needed to deal with the more complex data aggregation techniques used in many system architectures.
The new devices enhance the packet-processing capability of systems based on NPUs as processing elements.
Although an NPU might have sufficient capacity to regulate end-to-end traffic flow, the SPI-4 system backpressure creates "bursty" data that can interfere with the correct operation of these flow-control mechanisms.
Like all IDT packet-exchange devices, the SPI-4 family uses a backpressure scheme that tolerates a large range of logical port data rates.
Backpressure schemes are accommodated using large but efficient buffers created from segmented memory.
This results in faster response times and lower internal latency, while affording absorption of large external delays caused by data and flow-control pipelines in adjacent devices, such as packet-forwarding engines and PHY devices.
The buffering capabilities absorb typical bursts of in-flight packets and prevent loss of information that might occur as a result of long flow-control response times.
This backpressure scheme also helps to reduce the frequency of congestion and starvation cycles at points in the data path, resulting in more efficient flow of packet data.
The SPI-4 packet-exchange family offers a number of features, including the ability to perform an automatic dynamic deskew of a SPI-4 ingress data channel and SPI-4 egress status channel over a wide 80 to 450MHz range.
This feature centres ingress bits and words relative to the clock without intervention by the user.
In addition, the family offers a high-speed transceiver logic (HSTL) interface to QDR II memory or HSTL local packet interfacing to an ASIC or FPGA, thus enabling the expansion of on-chip memory in applications that require additional buffering.
Additionally, they offer a full suite of diagnostic counters and error simulators, which ease in-service diagnostics and automate system initialisation operations.
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