Product category:
Memory Devices and Modules
News Release from: IDT | Subject: IDT 72T36135
Edited by the Electronicstalk Editorial
Team on 17 December 2004
Larger FIFO offers easy upgrade path
Integrated Device Technology has released the industry's first 18Mbit TeraSync FIFO device.
Integrated Device Technology has released the industry's first 18Mbit TeraSync FIFO device The IDT 72T36135 operates at 225MHz
This article was originally published on Electronicstalk on 12 Apr 2001 at 8.00am (UK)
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The IDT 72T36135 replaces traditional methods of implementing high-density, high-speed buffering.
Previously, users would design a FIFO controller using a field programmable gate array (FPGA) coupled with an external SRAM.
This method was very costly, required additional board space and a lengthy design and validation cycle.
Such a design could achieve high-data throughput (8Gbit/s in and 8Gbit/s out) by going "massively parallel", resulting in the use of hundreds of costly FPGA I/Os and difficult and expensive routing of hundreds of I/O signals.
The new IDT 72T36135 reduces time to market by lessening the load on the FPGA designer.
The board-level designer's job becomes more simplistic because IDT offers the option of using one 18Mbit memory device in lieu of either two 9Mbit FIFOs or an FPGA plus SRAM solution.
The IDT 72T36135 contains a "mark and retransmit" feature that enables the user to set a read marker on the queue.
Mark and retransmit also allows data to be reread once from the queue or multiple times if retransmission of data is needed.
The IDT 72T36135 offers several value-added functions, such as user-selectable I/O on each port to simplify the interfacing of devices operating at different voltage levels, as well as bus matching, frequency matching, and programmable empty, partially empty, full and partially full flagging.
The IDT 72T36135 is available in a space-saving 240-PBGA package and is 50% smaller than previous two-chip solutions.
The device is backward pin-compatible with the company's existing 9Mbit TeraSync FIFO products, enabling an easy upgrade path with no board changes and allowing a designer to populate a design with a wide range of buffer capabilities in a single board layout.
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