Statistics engine offloads time-consuming tracking

The industry's first off-the-shelf statistics engine offloads the critical function of statistics tracking from processor elements such as NPUs, FPGAs and ASICs.

Integrated Device Technology has developed the industry's first off-the-shelf statistics engine.

Targeting edge router, broadband access equipment and multiservice provisioning platforms, the IDT statistics engine features a Network Processor Forum (NPF) Look Aside (LA-1) interface and offloads the critical function of statistics tracking from processor elements such as NPUs, FPGAs and ASICs.

With this new single-chip device, designers can focus on other compute-intensive functions related to meeting the requirements of IP-based services, including the transition from IPv4 to IPv6 and the deployment of content-rich services that tie revenue to comprehensive and accurate tracking of bandwidth consumption, such as streaming media and online gaming.

Edge and access equipment must maintain counters for thousands of customer flows, which is beyond the on-chip storage of today's NPUs and ASICs, thus requiring off-chip storage.

With today's internal processing elements operating in excess of 1GHz, stalling on multiple external clock read cycles per packet for flow statistics is very costly.

Stalls often require processor threads to context switch, further adding to complexity and overhead, which can exceed design budgets.

The IDT statistics engine uses an integrated 64bit arithmetic logic unit (ALU) designed to offload datapath processor cycles, typically resulting in a 90% improvement in network processor cycles required for statistics computation.

This allows designers to increase the line rate of packet processing and execute deeper packet inspection to support new IP-based services.

Equipment such as 10G (OC-192) edge/access/metro routers require differentiated services, and maintaining quality of service and service-level agreements at line rates with a single processor design is nearly impossible.

By preventing the processor element from stalling on the restrictive external bus transactions, the IDT statistics engine will play a critical role in helping customers overcome system-performance challenges.

The ALU coupled with the enhanced multiport memory cell architecture enables the statistics engine to update multiple counters with an innovative, patent-pending "fire-and-forget" operation.

"Fire and forget" is an atomic operation that replaces the conventional read-modify-write sequence, and allows the processor element to access and update as many as four counters on every clock cycle.

The benefits associated with the "fire-and-forget" function include up to 87% improvement in QDR-II bandwidth.

This feature will be especially useful to software designers who up until now, have relied on cycle consuming read-modify-write routines in their code.

The enhanced multiport memory cell architecture of the IDT statistics engine also ensures coherency for low latency statistics operations that require multiple statistics updates every 5ns, a capacity that becomes important at 10Gbit/s line rates and above.

The configurable 64/32bit ALU is also useful for systems that need to upgrade their legacy 32bit operations to 64bit operations without incurring performance penalties.

These configurable options, offering customers either 512K x 32bit counters or 256K x 64bit counters, allow the on-chip memory resources to be efficiently partitioned to match the system applications, such as traffic engineering and billing.

Because the statistics engine is a single-chip off-the-shelf solution, board designers realise benefits such as lower system costs, reduced board complexity and improved time to market.

In addition, the device's ability to "clamshell" to x18 burst-of-two QDR-II SRAM lends itself to ease of board design while addressing the emerging trend towards standardisation in network systems.

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