Product category:
Memory Devices and Modules
News Release from: IDT | Subject: 70T3719MG and 70T3799MG
Edited by the Electronicstalk Editorial
Team on 08 May 2006
Multiport memories suit 10Gbit/s systems
Supporting the bandwidth and performance requirements of next-generation wireless and networking infrastructures, IDT has added new products to its comprehensive portfolio of multiport devices.
Supporting the bandwidth and performance requirements of next-generation wireless and networking infrastructures, IDT has added new products to its comprehensive portfolio of multiport devices Among the new products are the industry's first true dual-port devices offering both x36 QDR-II or x18 LA-1 QDR-II interfaces, and a family of x72 synchronous dual-port devices
This article was originally published on Electronicstalk on 12 Apr 2001 at 8.00am (UK)
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Dual-port devices are used to facilitate communications between multiple processors by way of two ports integrating memory and logic control, enabling the processors simultaneous access to a common central memory.
These products are well-suited for wireless infrastructures, networking, storage, high-speed image processing and multicore computing, such as supercomputers.
The IDT QDR-II dual-port devices are available in both 9Mbit (70P3517 and 70P3337) and 18Mbit (70P3537 and 70P3307) densities and deliver 250MHz clock speed and 36Gbit/s in total throughput, enabling the products to achieve the necessary aggregate bandwidth common in 10Gbit/s applications, as well as allowing designers to realise faster communications between multiple processors.
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The products also offer a 1.8V core and selectable 1.4 and 1.9V I/O options for voltage matching between two separate domains.
HSTL I/O options are also available to support differing clock frequencies.
The JTAG interface allows designers to improve manufacturability with enhanced board debug and production diagnostics.
A "burst-of-2" capability enables the product to buffer two-word bursts on all accesses.
The burst-of-2 data transfer capability creates lower bus latency and therefore provides more flexibility for the host controller than data transfers that use longer burst lengths.
The QDR-II interface suits datapath acceleration as it provides independent buses for reading and writing on each port.
Reads and writes can take place simultaneously, which is not possible on single duplex buses that require some amount of "dead" time to turn the bus from read to write or write to read.
This optimisation makes the IDT QDR-II dual ports ideal for low latency and high-speed interconnect between ASICs.
Delivering 166MHz performance, the IDT 70T3719MG 18Mbit (256K x 72bit) and 70T3799MG 9Mbit (128K x 72bit) dual-port devices support the 64bit memory interfaces found in next-generation digital signal processors (DSPs) with a single-chip solution, thereby reducing design cost, complexity and component count.
The devices offer a host of synchronous functions, such as full-boundary counters, multiple independent chip and byte enables, collision detect signal and synchronous interrupts.
They are also equipped with an optional sleep mode on both ports, which allows the product to minimise power consumption by placing the part in full standby mode without any input-level restrictions.
In addition, designers can activate the products' sleep mode function by programming a single pin.
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