Dielectric research extended

IMEC has extended its industrial affiliation programme on high-k dielectrics for sub-65nm devices to provide solutions for the implementation of metal gate stacks in planar scaled CMOS.

IMEC has extended its industrial affiliation programme (IIAP) on high-k dielectrics for sub-65nm devices to provide solutions for the implementation of metal gate stacks in planar scaled CMOS.

The implementation of high-k stacks with polysilicon electrodes is currently being pursued at IMEC, starting from a baseline process with 65nm gate length transistors and dielectric layers with an EOT (equivalent oxide thickness) in the range of 1.6 to 1.4nm, targeting applications where low gate leakage is required.

However, scaling of polysilicon gate stacks with EOT of 1nm and below gives rise to serious concerns for the yield and reliability of these layers.

This necessitates the introduction of metal gate electrodes for advanced applications.

The activities on the implementation of metal gates will start from a 45nm process platform.

Both single and dual metal gate options will be pursued and implemented in CMOS devices with a gate length of 20nm (and below if feasible).

Hf-based high-k dielectric layers with EOT levels around 1nm will be used at the start of the program.

Gradually, the EOT and gate dimensions will be decreased and the related limitations will be investigated.

The final realisation of the programme aims at sub-20nm transistors with dielectric stacks having EOT values close to 0.5nm.

To this purpose, the possible integration of alternative high-k dielectrics with k values that exceed the range that can currently be obtained with Hf-based materials, may have to be considered.

"Since 2000 we have built up extensive experience in the area of high-k gate stacks through our IIAPs, in which a worldwide consortium of the world's semiconductor manufacturers collaborate to find a replacement for conventional gate stack materials.

The metal gate program builds on our expertise developed in both the high-k and 'HikDIP' IIAPs, which aim to solve the problems arising when integrating high-k gate dielectric and polysilicon gate stack CMOS", said Gilbert Declerck, President and CEO of IMEC.

"Partners in this program will be able to benefit from this experience and use IMEC's state-of-the-art equipment to develop CMOS devices scaled to the ultimate limits".

The programme is scheduled to start in mid 2003 and is expected to run until the end of 2006.

Target partners are leading semiconductor manufacturers worldwide, whether they already participate in the high-k IIAP or not.

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