Tool produces optimised memory architectures

Edited by the Electronicstalk editorial team Apr 29, 2003

The novel Atomium/MemoryArchitect tool can help design the perfect memory architecture for multimedia and telecommunications applications.

IMEC's new Atomium/MemoryArchitect tool helps to design the perfect memory architecture for multimedia and telecommunications applications.

This extension of IMEC's Atomium toolsuite (a toolbox for optimising memory I/O using geometrical models) is the first memory synthesis and mapping tool that is able to handle complex applications under real-life constraints.

In many applications, data storage and the transfer of data to/from memory are the main bottlenecks in terms of performance, power and silicon area.

Therefore, the design of an optimised memory architecture is essential for a low-cost solution.

Current state-of-the-art memory synthesis and mapping is based on ad hoc methods to arrive at a memory architecture.

The lack of a formalised methodology and tool support restricts the process of exploring the range of solutions available and much better results could be obtained with tools that support these design steps.

Until now, memory synthesis and mapping tools that can handle applications with industrial complexity and under real-life constraints have not been available.

To address this need, IMEC has developed the Atomium/MemoryArchitect tool.

It defines an optimised memory architecture (in terms of power, area, number of memories etc) for a specific application, providing sufficient memory bandwidth to meet the application's real-time constraints.

The MemoryArchitect tool also allows designers to obtain fast and accurate cost estimates for the memory requirements of any application written in ANSI-C.

The MemoryArchitect tool accepts the following inputs: the application specified in ANSI-C; timing constraints for the application; a user definable library characterising the memory modules it can use; profiling information; and a (user-definable) assignment of data to memory hierarchy layers.

From this input the tool computes the following results: an optimised memory allocation for each hierarchy layer (how many memories, how many ports on each memory, the word width of each memory etc); an optimised assignment of all the data to memory modules (which array has to be stored in which memory module); absolute cost estimates for the memory architecture (power, silicon area, performance, number of memories, number of ports etc); and an optimised distribution of the available time budget over the different loops and functions of the application.

Moreover, the MemoryArchitect tool does not just provide a single solution but provides a whole set of Pareto-optimal solutions from which the designer can choose.

This allows the designer to make well informed trade-off decisions (eg tradeoff silicon area for less power consumption).

The Atomium toolsuite comes with a highly intuitive graphical user interface with several views that can help the designer to optimise the memory-related aspects of the application.

The design environment is available for industrial partners in IMEC's industrial affiliation program (IIAP) on MPEG-4 and SoC++.

Atomium/MemoryArchitect has been successfully applied on an MPEG-4 video encoder and decoder, a wavelet image compressor, a turbo decoder and other multimedia and telecommunication applications.