Materials research aims for sub-45nm processes

IMEC has launched two industrial affiliation programmes targeting sub-45nm technology generations.

IMEC has launched two industrial affiliation programmes (IIAPs) targeting sub-45nm technology generations.

The first programme aims at providing solutions for improved device performance by implementing strained silicon (Si) in the transistor channel for scaled planar MOS devices.

The second programme will exploit the high-mobility features of germanium (Ge) to fabricate high-performance CMOS transistors.

The programmes are interlinked with IMEC's present advanced CMOS research programmes, which aim at developing the enabling process and device technologies for future technology generations.

Within the first programme, "Implementation of high-mobility layers and advanced source/drain engineering solutions in scaled planar devices", the introduction of strained silicon will be investigated to improve carrier mobility.

The research covers strained silicon formation on top of SRB (strain relaxed buffer) layers, silicide formation, shallow junctions and extensions, compatibility issues, advanced strain characterisation and device demonstration.

Within this programme, partners can benefit from major breakthroughs that IMEC has already achieved in the area of strained silicon on SiGe transistors, ultrashallow junctions and silicides.

As such IMEC has developed an innovative production technique for thin SRBs with a total thickness of less than about 200nm and with superior properties compared with the industry standard.

Moreover, this SRB technique can also be applied in a selective way on preformed isolation structures such as STI (shallow-trench isolation).

Besides that, IMEC has shown world-record mobility figures for holes in hetero-pMOS with strained SiGe.

The second programme will explore a germanium-based technology to fabricate high-performance CMOS transistors in a process compatible with silicon baseline CMOS.

Germanium has recently regained significant interest within the semiconductor industry due to its attractive properties such as high mobility and compatibility with high-k materials.

These features make germanium CMOS devices ideally suited for high-performance, low power circuits with improved performance when compared to advanced strained silicon layers.

The germanium CMOS devices programme targets the feasibility demonstration of fabricating germanium devices compatible with a state-of-the-art silicon production line.

These germanium devices will include high-k materials and metal gates to obtain aggressively scaled EOT (equivalent oxide thickness) targets.

Ultimately, the programme aims at the fabrication of high-performance CMOS transistor structures in germanium that can be used for future technology generations.

These innovative programmes will be closely interlinked with IMEC's current advanced material, process steps and models research programmes targeting the sub-45nm technology node, including: advanced lithography programme; implementation of high-k dielectrics and metal gates in scaled planar devices; emerging CMOS devices for future technology generations (fully depleted silicon-on-insulator, multigate FETs); advanced interconnect solutions; and cleaning and contamination control.

The programmes are initially using 200mm equipment but will gradually transfer to 300mm equipment in IMEC's new facility now under construction.

The move to 300mm will guarantee that the advanced research is at least two generations ahead of industrial requirements.

In addition, this centralised research process platform will serve various industry alliances.

In this way, IMEC and its research partners can optimise the return on investments associated with the high increased costs of 300mm technology.

Potential partners are leading IC and wafer manufacturers.

These companies will benefit from IMEC's long tradition and track record in process module and advanced device research focused on module implementation issues and from IMEC's unique business model which is based on a sharing of cost, risk, talent and intellectual property.

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