Programme on reconfigurable multiprocessor systems

A new research programme aims to develop a flexible power-efficient architecture and easy design flow for future wireless and multimedia systems.

Building on its previous work in reconfigurable systems, IMEC has begun a new research programme targeting a flexible power-efficient architecture and easy design flow for future wireless and multimedia systems.

Research results now include an IMEC-developed architecture template combining a VLIW DSP and coarse-grained array, and a prototype C compiler which enables easy programming of the architecture.

Combining a very long instruction word (VLIW) DSP with a coarse-grained array, IMEC has developed a power-efficient flexible architecture template and a retargetable compiler for coarse-grained reconfigurable processors.

The VLIW DSP efficiently executes control-flow code by exploiting instruction-level parallelism.

The array, containing many function units, accelerates data-flow loops by exploiting high degrees of loop-level parallelism.

The architecture template allows designers to specify the interconnection, type and number of function units.

The C compiler targets both the VLIW processor and the array.

Application source code can therefore be compiled directly onto the coarse-grained reconfigurable processor.

This architectural flexibility and C design flow allows a designer to rapidly explore architectural options for an application domain.

IMEC's novel processor provides a unique combination of benefits.

Applications can be designed completely in C as the compiler-friendly architectural features provide the programmability and flexibility of a processor.

The processor has the high performance, low power and flexibility of a traditional coarse-grained array.

Coarse-grained arrays have higher performance and lower power consumption compared to a processor as many more execution units operate in parallel and distributed register files in the array reduce data transfers.

There are also performance and power improvements over traditional coarse-grained arrays thanks to the tight coupling of the VLIW processor and the array, which reduces the number of data transfers.

So far, IMEC has a functioning prototype retargetable compiler and ongoing research in benchmarking the architecture in terms of power, performance and area.

Initial results are available for a MPEG-2 decoder mapped on an array of 64 function units, showing a speed improvement of a factor of three over a VLIW processor.

Future research will focus on improving the memory hierarchy, developing the control path and a systematic architectural exploration methodology.

IMEC's research and development (R and D) programme targets future wireless and multimedia applications that will require high-performance processors characterised by highly flexible architectures and low power consumption.

The processors must be flexible enough to support rapidly changing applications and standards without modifying the hardware.

At the same time, they must provide the demanding performance required by the applications and prolong battery lifetime.

Existing solutions cannot provide all of these properties.

Digital signal processors (DSPs) are flexible and easy to program using high-level programming languages, but they do not feature the high performance and power-efficiency of customised processors and application-specific integrated circuits (ASICs).

Coarse-grained arrays are flexible and have high performance but are difficult to program.

Access to this technology can be obtained through participation in IMEC's research programme on reconfigurable multiprocessor systems.

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