Rad-hard library gains novel output driver

Adiabatic Logic has signed a co-operation agreement with IMEC, which will lead to its patented low power intelligent output driver technology being used by IMEC in radiation hardened environments.

Adiabatic Logic has signed a co-operation agreement with IMEC, which will lead to its patented low power intelligent output driver (IOD) technology being used by IMEC in radiation hardened environments, such as in space applications, where power optimisation is imperative.

Adiabatic Logic's IOD IP cell is designed to replace the conventional pad drivers in an IC and uses a patented energy recycling technique, which delivers 50-75% power savings in chip I/O for portable devices such as laptops, smartphones, handheld computers, digital cameras and MP3 players.

"This is a significant agreement for Adiabatic Logic as IMEC is a world class research organisation which, like Adiabatic Logic, is focused on reducing power in electronics systems", said Simon Payne, Adiabatic Logic's Chief Executive Officer.

"We are delighted that IMEC has recognised the power saving potential of IOD by incorporating our driver into its library of radiation hardened 180nm technology".

IMEC's design against radiation effects (DARE) library consists of 60 core cells, 32 input/output cells (including LVDS) with enhanced ESD performance and an SRAM compiler as well as a PLL.

The first ASIC designed and manufactured using the library is functional.

Radiation test results will become available in the first quarter of 2004.

Commenting on the agreement, Professor Herman E Maes, IMEC Vice-President, said: "Power optimisation is one of the key challenges facing today's electronics industry and IMEC wants to play a major role in this field.

Co-operating with companies with innovative solutions like Adiabatic Logic will ensure that we achieve our objective".

Adiabatic Logic's IOD uses the speed of submicron CMOS to actively mimic the voltage-current drive characteristics of a classic driver with a source (or series) terminator resistor.

It does this in such a way that the bulk of the current is delivered to the load capacitance nonresistively from a reservoir capacitance maintained at a mid rail voltage, assisted by the inherent inductance of the load.

The on-chip reservoir capacitance delivers charge on rising edges and recovers charge on falling edges thereby recycling energy, which is conventionally wasted.

"IOD's substantial power saving capability is clearly what attracted us to this technology", said Steven Redant, an ASIC Design Manager at IMEC.

"It's a clever piece of IP which, if it can withstand the effects of radiation, will be an important addition to our DARE library".

Adiabatic Logic's IOD solution, offers a multitude of other potential benefits to IC and system developers in addition to power saving.

For example, it can reduce the overall component count and bill of material (BOM) cost by minimising battery size, cutting DC/DC convertor/thermal management costs and eliminating the requirement for terminating resistors.

The first silicon implementation of IOD was completed in October 2003 using a 0.6-micron process technology.

The results showed power savings of more than 50% compared with traditional I/O schemes.

"The power saving results from our first test chips and now this endorsement from IMEC will provide a major boost to our licensing efforts", added Geoff Harvey, Chief Technology Officer at Adiabatic Logic.

"We hope to see IOD-enabled integrated circuits being used in electronics systems in the very near future".

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