Research investigates future embedded RAM schemes

IMEC is seeking industrial partners and research centres to participate in a new industrial affiliation programme on embedded RAM concepts for second and higher levels of on-chip cache memory.

IMEC is seeking industrial partners and research centres to participate in a new industrial affiliation programme on embedded RAM concepts for second and higher levels of on-chip cache memory.

The research programme, which focuses on the 45nm node and below, will addresss three concepts: direct tunnelling RAM; ferroelectric field effect transistors; and floating body cells.

The three concepts will be implemented in silicon by year-end to demonstrate their feasibility.

The first concept of direct-tunnelling RAM uses a very thin (around 1.5nm) oxide Flash structure in which charge can be stored on either a floating gate or on a charge-trapping layer.

In both cases, the use of high-k materials is being considered as well to lower the write/erase voltages.

First simulation results of the expected threshold voltage window for different combinations of voltages and tunnel oxide thicknesses, as obtained from IMEC's tunnelling model, evidence the feasibility of a 10ns programming time at the 45nm node.

The second concept, the ferroelectric field effect transistor (FeFET) recently regained a lot of attention because of its superior scalability as compared to the capacitor-based ferroelectric RAM.

Also here, the advantage of using high-k materials is substantial since they can be used as a buffer layer between the channel and the ferroelectric in order to lower the write/erase voltages.

The third concept is based on the floating body cell, a concept based on the memory effect in silicon-on-insulator (SoI) devices initially developed at IMEC back in 1988.

The technology is being adapted for planar as well as FinFET device structures.

Preliminary retention results, obtained on partially depleted SoI MOSFETs programmed by impact ionisation, show the memory effect in scaled-down SoI technology.

In all of these cases, IMEC has a longstanding background and expertise guaranteeing that results can be generated within a very short time frame of six to 18 months.

The eRAM project complements IMEC's Flash memory project which began in 2000.

IMEC's eRAM programme has been started in order to answer the urgent need for a new embedded RAM concept for second and higher levels of on-chip cache memory.

Fast first-level cache memory which has been, and probably will continue to be, addressed by static RAMs are reaching their scaling limits already today due to their drastic increase in relative cell size.

As most IC applications will need relatively large amounts of on-chip memory, their footprint is expected to increase to 80-90% of the chip area in some of these major applications.

At the same time, embedded dynamic RAM has never been widely accepted as a mainstream technology option because of limited availability, process complexity and cost issues.

The technology that is being developed within IMEC's programme neither aims to replace the first-level cache (SRAM), nor the (eventual) embedded nonvolatile Flash or read-only memory (ROM) blocks.

Rather the large blocks of volatile memory required in future applications are targeted in order to reduce overall memory footprints and hence realise huge cost savings for a wide range of IC products.

The eRAM IIAP is a complementary research program to IMEC's Flash Memory IIAP (running since 2000) within IMEC's newly established Advanced Memory Programme.

IMEC is inviting participation in the programme by leading IC manufacturers.

IMEC Industrial Affiliation programmes offer partners the advantages of both reduced costs and early process knowledge.

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